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Original file line number Diff line number Diff line change
Expand Up @@ -422,8 +422,12 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,

APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth);
KnownBits InputKnown(SrcBitWidth);
if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1)) {
// For zext nneg, we may have dropped the instruction which made the
// input non-negative.
I->dropPoisonGeneratingFlags();
return I;
}
assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?");
Known = InputKnown.zextOrTrunc(BitWidth);
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
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4 changes: 1 addition & 3 deletions llvm/test/Transforms/InstCombine/zext.ll
Original file line number Diff line number Diff line change
Expand Up @@ -779,11 +779,9 @@ define i64 @evaluate_zexted_const_expr(i1 %c) {
ret i64 %ext
}

; FIXME: This is currently miscompiling as the and gets dropped,
; but the flag on the zext doesn't.
define i16 @zext_nneg_flag_drop(i8 %x, i16 %y) {
; CHECK-LABEL: @zext_nneg_flag_drop(
; CHECK-NEXT: [[EXT:%.*]] = zext nneg i8 [[X:%.*]] to i16
; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[X:%.*]] to i16
; CHECK-NEXT: [[OR1:%.*]] = or i16 [[EXT]], [[Y:%.*]]
; CHECK-NEXT: [[OR2:%.*]] = or i16 [[OR1]], 128
; CHECK-NEXT: ret i16 [[OR2]]
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