- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[SLP]Exclude non-profitable subtrees. backend:NVPTX backend:RISC-V llvm:transforms vectorizers
#162018 opened Oct 5, 2025 by alexey-bataev Loading… updated Nov 28, 2025
[RISCV] Update SpacemiT-X60 vector load/stores backend:RISC-V
#169936 opened Nov 28, 2025 by mikhailramalho Loading… updated Nov 28, 2025
[RISCV]: Implemented softening of SelectionDAGISel as well
FCANONICALIZE backend:RISC-V llvm:SelectionDAG #169234 opened Nov 23, 2025 by kper Loading… updated Nov 28, 2025
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading… updated Nov 28, 2025
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading… updated Nov 28, 2025
[RISCV] Add Svrsw60t59b extension backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:mc Machine (object) code
#132321 opened Mar 21, 2025 by trdthg Loading… updated Nov 28, 2025
[RISCV][GISel] Fix legalize G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169877 opened Nov 28, 2025 by jacquesguan Loading… updated Nov 28, 2025
[VPlan] Sink recipes from the vector loop region in licm. backend:RISC-V llvm:transforms vectorizers
#168031 opened Nov 14, 2025 by Mel-Chen Loading… updated Nov 28, 2025
[clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category
#110690 opened Oct 1, 2024 by KamranYousafzai Loading… updated Nov 27, 2025
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading… updated Nov 27, 2025
[RISCV][GISel] Support select G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169789 opened Nov 27, 2025 by jacquesguan Loading… updated Nov 27, 2025
[RISCV][WIP] Let RA do the CSR saves. backend:RISC-V
#90819 opened May 2, 2024 by mgudim Loading… updated Nov 27, 2025
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading… updated Nov 27, 2025
[VPlan] Don't use the legacy cost model for loop conditions backend:RISC-V llvm:transforms vectorizers
#156864 opened Sep 4, 2025 by john-brawn-arm Loading… updated Nov 26, 2025
[DAG] Fold mul 0 -> 0 when expanding mul into parts. backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#168780 opened Nov 19, 2025 by davemgreen Loading… updated Nov 26, 2025
[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading… updated Nov 26, 2025
[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. backend:RISC-V
#169529 opened Nov 25, 2025 by topperc Loading… updated Nov 26, 2025
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading… updated Nov 26, 2025
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading… updated Nov 25, 2025
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading… updated Nov 25, 2025
[RISCV64] liveness analysis backend:RISC-V llvm:regalloc
#167454 opened Nov 11, 2025 by hiraditya Loading… updated Nov 24, 2025
[FMV][AArch64] Allow user to override version priority. backend:AArch64 backend:ARM backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms tablegen
#150267 opened Jul 23, 2025 by labrinea Loading… updated Nov 24, 2025
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading… updated Nov 24, 2025
[LV] Convert uniform-address unmasked scatters to scalar store. backend:RISC-V llvm:transforms vectorizers
#166114 opened Nov 3, 2025 by ElvisWang123 Loading… updated Nov 24, 2025
[RISCV][LLD] Zcmt RISC-V extension in lld backend:RISC-V lld:ELF lld
#163142 opened Oct 13, 2025 by RobinKastberg Loading… updated Nov 22, 2025
5 of 8 tasks
ProTip! Adding no:label will show everything without a label.