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Pull requests: llvm/llvm-project
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[llvm][RISCV] Make X0 register pair legal in pre-ra pass backend:RISC-V
#169164 opened Nov 22, 2025 by 4vtomat Loading… updated Nov 22, 2025
[CodeGen] Allow multiple location for the same CSR. backend:RISC-V llvm:codegen
#168531 opened Nov 18, 2025 by mgudim Loading… updated Nov 21, 2025
[lldb][RISCV] Implement trap handler unwind plan backend:RISC-V lldb
#166531 opened Nov 5, 2025 by sga-sc Loading… updated Nov 21, 2025
[RISCV] Introduce a new tune feature string syntax and its parser backend:RISC-V tablegen
#168160 opened Nov 15, 2025 by mshockwave Loading… updated Nov 21, 2025
[RISCV][NO-MERGE] Discussions on passing tuning features from the Clang driver backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#162716 opened Oct 9, 2025 by mshockwave Loading… updated Nov 20, 2025
[RISCV] Expand
X * (2^N - 2^M) where N < M backend:RISC-V #168843 opened Nov 20, 2025 by pfusik Loading… updated Nov 20, 2025
[RISCV] Implement RVV scheduling model for andes 45 series processor. backend:RISC-V
#167821 opened Nov 13, 2025 by tclin914 Loading… updated Nov 20, 2025
[RISCV] Implement Clang Builtins for XAndesPerf Extension backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category llvm:ir
#147018 opened Jul 4, 2025 by tclin914 Loading… updated Nov 20, 2025
[IR] Add llvm SelectionDAGISel as well
clmul intrinsic backend:RISC-V llvm:ir llvm:SelectionDAG #140301 opened May 16, 2025 by oscardssmith Loading… updated Nov 19, 2025
[RISCV] Mark sincos libcalls as available for RISC-V backend:RISC-V llvm:ir
#168708 opened Nov 19, 2025 by asb Loading… updated Nov 19, 2025
[CodeGen] Check physical def kill flag in MachineInstr::isDead backend:RISC-V llvm:codegen
#168684 opened Nov 19, 2025 by lukel97 Loading… updated Nov 19, 2025
[SLP]Initial support for non-power-of-2 vectorization backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#151530 opened Jul 31, 2025 by alexey-bataev Loading… updated Nov 18, 2025
[RISCV][llvm-objdump] Support --symbolize-operands backend:RISC-V llvm:binary-utilities
#166656 opened Nov 5, 2025 by lenary Loading… updated Nov 17, 2025
[LoopVectorize][LAA] Hoist load in memory IV to allow vectorization backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168312 opened Nov 17, 2025 by felipealmeida Loading… updated Nov 17, 2025
DAG: Use poison for some load/store offsets in legalizer backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167756 opened Nov 12, 2025 by arsenm Loading… updated Nov 15, 2025
[LV][RFC] Generating conditional VPBB that will be skip when the mask is inactive in VPlan. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#141900 opened May 29, 2025 by ElvisWang123 Loading… updated Nov 14, 2025
[DAGCombine] Invert vselect to make TrueValue is binop backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#167499 opened Nov 11, 2025 by ChunyuLiao Loading… updated Nov 13, 2025
[VPlan] Narrow VPWidenCastRecipe to scalar cast recipe. backend:RISC-V llvm:transforms vectorizers
#166514 opened Nov 5, 2025 by Mel-Chen Loading… updated Nov 12, 2025
DAG: Handle load in SimplifyDemandedVectorElts backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:NVPTX backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#122671 opened Jan 13, 2025 by arsenm Loading… updated Nov 12, 2025
[ConstantFolding] Stop folding NaNs backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms
#167475 opened Nov 11, 2025 by spavloff Loading… updated Nov 12, 2025
[VPlan] Move addExplicitVectorLength to tryToBuildVPlanWithVPRecipes backend:RISC-V llvm:transforms vectorizers
#166164 opened Nov 3, 2025 by lukel97 Loading… updated Nov 11, 2025
[GlobalISel] Port computeNumSignBits for G_MUL backend:AArch64 backend:RISC-V llvm:globalisel
#167311 opened Nov 10, 2025 by AnushaK6 Loading… updated Nov 11, 2025
[libc][math] Implement C23 half precision pow function backend:AMDGPU backend:RISC-V libc
#159906 opened Sep 20, 2025 by AnonMiraj Loading… updated Nov 9, 2025
[ConstantTime][LLVM] Add llvm.ct.select intrinsic with generic SelectionDAG lowering backend:RISC-V backend:X86 llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#166702 opened Nov 6, 2025 by wizardengineer Loading… updated Nov 8, 2025
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