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Pull requests: llvm/llvm-project
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[LV] Convert uniform-address unmasked scatters to scalar store. backend:RISC-V llvm:transforms vectorizers
#166114 opened Nov 3, 2025 by ElvisWang123 Loading…
Refactor WIDE_READ to allow finer control over high-performance function selection backend:RISC-V bazel "Peripheral" support tier build system: utils/bazel libc
#165613 opened Oct 29, 2025 by Sterling-Augustine Loading…
[clang][RISCV] Add big-endian RISC-V target support backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#165599 opened Oct 29, 2025 by djtodoro Loading…
[CodeGen][PreISelIntrinsicLowering] Add VP-based lowering for memcpy/memmove/memset backend:NVPTX backend:RISC-V backend:SPIR-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#165585 opened Oct 29, 2025 by dadra-oc Loading…
[GlobalISel] Rename G_ABDS/G_ABDU to G_SABD/G_UABD backend:AArch64 backend:RISC-V llvm:globalisel llvm:support mlgo
#165236 opened Oct 27, 2025 by davemgreen Loading…
[CodeGen] Test LICM behaviour on loop invariant loads. backend:RISC-V
#165025 opened Oct 24, 2025 by mgudim Loading…
[DAG] SimplifyDemandedBits - ICMP_SLT(X,0) - only sign mask of X is required backend:AArch64 backend:AMDGPU backend:loongarch backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#164946 opened Oct 24, 2025 by an1k3sh Loading…
[llvm-exegesis][RISCV] Deflake rvv/filter.test: split e8/e16 paths and handle empty-snippet case (ALLOW_RETRIES:1) backend:RISC-V tools:llvm-exegesis
#164924 opened Oct 24, 2025 by hank95179 Loading…
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading…
[RISCV] Support Zvfofp4min assembler version 0.1 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#164820 opened Oct 23, 2025 by 4vtomat Loading…
[RISCV] Add a test showing that scalable offsets are not handled. backend:RISC-V
#164480 opened Oct 21, 2025 by mgudim Loading…
[VPlan] Replace ExtractLast(Elem|LanePerPart) with ExtractLast(Lane/Part) backend:RISC-V llvm:transforms vectorizers
#164124 opened Oct 18, 2025 by fhahn Loading…
[libc][stdlib][annex_k] Add set_constraint_handler_s. backend:RISC-V libc
#164093 opened Oct 18, 2025 by bassiounix Loading…
[libc][stdlib][annex_k] Add ignore_handler_s. backend:RISC-V libc
#164090 opened Oct 18, 2025 by bassiounix Loading…
[libc][annex_k] Add abort_handler_s. backend:RISC-V libc
#164089 opened Oct 18, 2025 by bassiounix Loading…
[lldb][RISCV] Fix return value reading backend:RISC-V lldb
#163931 opened Oct 17, 2025 by sga-sc Loading…
[clang] Ensure -mno-outline adds attributes backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#163692 opened Oct 16, 2025 by lenary Loading…
[clang][Driver] Support Outline Flags on RISC-V and X86 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#163664 opened Oct 16, 2025 by lenary Loading…
[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size backend:RISC-V
#163501 opened Oct 15, 2025 by tclin914 Loading…
[RISCV][LLD] Zcmt RISC-V extension in lld backend:RISC-V lld:ELF lld
#163142 opened Oct 13, 2025 by RobinKastberg Loading…
5 of 8 tasks
[FPEnv][SDAG] Implement FNEARBYINT with optional chain backend:AArch64 backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#163081 opened Oct 12, 2025 by spavloff Loading…
[DAGCombiner][X86] Push bitcast/ext through freeze for loads backend:AArch64 backend:AMDGPU backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#163070 opened Oct 12, 2025 by guy-david Loading…
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading…
[RISCV][NO-MERGE] Discussions on passing tuning features from the Clang driver backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#162716 opened Oct 9, 2025 by mshockwave Loading…
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