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Pull requests: llvm/llvm-project
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[AMDGPU] Update log lowering to remove contract for AMDGCN backend backend:AMDGPU
#168916 opened Nov 20, 2025 by adelejjeh Loading… updated Nov 26, 2025
[AMDGPU] Sink uniform buffer address offsets into soffset backend:AMDGPU
#169230 opened Nov 23, 2025 by PrasoonMishra Loading… updated Nov 26, 2025
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses backend:AMDGPU llvm:globalisel
#162580 opened Oct 9, 2025 by doru1004 Loading… updated Nov 26, 2025
[AMDGPU] IGLP: Fix static variables backend:AMDGPU
#137549 opened Apr 27, 2025 by ro-i Loading… updated Nov 26, 2025
[AMDGPU] Refactor GFX11 VALU Mask Hazard Waitcnt Merging backend:AMDGPU
#169213 opened Nov 23, 2025 by perlfu Loading… updated Nov 26, 2025
[AMDGPU][GISel] Add RegBankLegalize support for G_SI_CALL backend:AMDGPU llvm:globalisel
#165747 opened Oct 30, 2025 by chinmaydd Loading… updated Nov 26, 2025
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading… updated Nov 26, 2025
VectorCombine: Improve the insert/extract fold in the narrowing case backend:AMDGPU llvm:transforms llvm:vectorcombine vectorizers
#168820 opened Nov 20, 2025 by nhaehnle Loading… updated Nov 25, 2025
Use register pair for PC spill backend:AMDGPU llvm:globalisel
#169098 opened Nov 21, 2025 by slinder1 Loading… updated Nov 25, 2025
[AMDGPU] Modifies builtin def to take _Float16('x') for both HIP/C++ and for OpenCL backend:AMDGPU clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#167652 opened Nov 12, 2025 by ranapratap55 Loading… updated Nov 25, 2025
[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short backend:AMDGPU llvm:globalisel
#167798 opened Nov 13, 2025 by mssefat Loading… updated Nov 25, 2025
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading… updated Nov 25, 2025
[AMDGPU][NFC][SIInsertWaitcnts] Remove redundant checks for invalidate instructions backend:AMDGPU
#166139 opened Nov 3, 2025 by stepthomas Loading… updated Nov 25, 2025
[AMDGPU] Add machine-level inliner pass backend:AMDGPU testing-tools
#169476 opened Nov 25, 2025 by rovka Loading… updated Nov 25, 2025
[AMDGPU] Insert inliner anchor earlier backend:AMDGPU llvm:codegen
#169478 opened Nov 25, 2025 by rovka Loading… updated Nov 25, 2025
[AMDGPU] Update machine frame info during inlining backend:AMDGPU
#169477 opened Nov 25, 2025 by rovka Loading… updated Nov 25, 2025
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading… updated Nov 25, 2025
[Clang] Default to async unwind tables for amdgcn backend:AMDGPU clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#166464 opened Nov 4, 2025 by slinder1 Loading… updated Nov 24, 2025
[AMDGPU] Enabled machine scheduler option amdgpu-use-amdgpu-trackers. backend:AMDGPU llvm:globalisel
#169187 opened Nov 22, 2025 by dhruvachak Loading… updated Nov 24, 2025
[AMDGPU] Allow folding of non-subregs through REG_SEQUENCE backend:AMDGPU
#151033 opened Jul 28, 2025 by JoshHuttonCode Loading… updated Nov 24, 2025
[AMDGPU] Make rotr illegal backend:AMDGPU
#166558 opened Nov 5, 2025 by jayfoad Loading… updated Nov 24, 2025
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading… updated Nov 24, 2025
[AMDGPU] Allow any SGPRs for chain callees backend:AMDGPU llvm:globalisel
#168345 opened Nov 17, 2025 by rovka Loading… updated Nov 24, 2025
[IndVarSimplify] Remove sinkunusedInvariants backend:AMDGPU llvm:transforms
#169250 opened Nov 23, 2025 by VigneshwarJ Loading… updated Nov 23, 2025
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads backend:AMDGPU llvm:globalisel
#168917 opened Nov 20, 2025 by arsenm Loading… updated Nov 21, 2025
ProTip! What’s not been updated in a month: updated:<2025-11-01.