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Pull requests: llvm/llvm-project
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[RISCV] Enable (non trivial) remat for most scalar instructions backend:RISC-V llvm:globalisel
#162311 opened Oct 7, 2025 by preames Loading…
[SLP]Exclude non-profitable subtrees. backend:NVPTX backend:RISC-V llvm:transforms vectorizers
#162018 opened Oct 5, 2025 by alexey-bataev Loading…
[libc][math][c++23] Add expbf16 math function backend:AMDGPU backend:RISC-V libc
#161919 opened Oct 3, 2025 by krishna2803 Loading…
[VectorUtils] Check wrap with assume in analyzeInterleaving backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
[DAG] Use known-bits when creating umulh/smulh. backend:AMDGPU backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#160916 opened Sep 26, 2025 by davemgreen Loading…
[GlobalMerge] Convert GlobalMerge to a ModulePass backend:AArch64 backend:ARM backend:PowerPC backend:RISC-V llvm:codegen
#160703 opened Sep 25, 2025 by asb Loading…
[bolt][riscv] Fix conditional tail call backend:RISC-V BOLT
#160042 opened Sep 22, 2025 by zengdage Loading…
[libc][math] Implement C23 half precision pow function backend:AMDGPU backend:RISC-V libc
#159906 opened Sep 20, 2025 by AnonMiraj Loading…
[RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced backend:RISC-V
#159715 opened Sep 19, 2025 by ChunyuLiao Loading…
[VPlan] Use BlockFrequencyInfo in getPredBlockCostDivisor backend:RISC-V llvm:transforms vectorizers
#158690 opened Sep 15, 2025 by lukel97 Loading…
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading…
[RISCV] Remove experimental from Zicfilp and Zicfiss backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#157015 opened Sep 5, 2025 by tclin914 Loading…
[VPlan] Don't use the legacy cost model for loop conditions backend:RISC-V llvm:transforms vectorizers
#156864 opened Sep 4, 2025 by john-brawn-arm Loading…
[RISCV][TTI] Fix shift VV opcode mapping in getArithmeticInstrCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#156408 opened Sep 2, 2025 by steven-studio Loading…
[RISCV] Fix shift instruction opcodes in getArithmeticInstrCost backend:RISC-V
#156335 opened Sep 1, 2025 by steven-studio Loading…
[libc] Add support for std::cout on embedded backend:RISC-V libc
#156330 opened Sep 1, 2025 by saturn691 Loading…
[DAGCombiner] Add pattern matching for negated subtraction in ABDU selection backend:AArch64 backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#156217 opened Aug 31, 2025 by AZero13 Loading…
[RISCV] Eagerly optimize scalar packing for buildvector lowering backend:RISC-V
#156062 opened Aug 29, 2025 by preames Loading…
[RISCV] Use C.ADD when OR is not compressible due to register restriction backend:RISC-V
#156044 opened Aug 29, 2025 by preames Loading…
[RISCV] Simplify Zcf/Zce/Zcd Predicates backend:RISC-V
#155035 opened Aug 22, 2025 by lenary Loading…
[SelectionDAG] Use Magic Algorithm for Splitting UDIV/UREM by Constant backend:AArch64 backend:ARM backend:MIPS backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#154968 opened Aug 22, 2025 by mskamp Loading…
[Driver][Gnu] Auto-link libstdc++fs for GCC versions in [5.3, 9.2) backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#154826 opened Aug 21, 2025 by yxsamliu Loading…
[RISCV] Early exit if the type legalization cost is not valid for getIntrinsicInstrCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#154256 opened Aug 19, 2025 by tclin914 Loading…
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