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Move SI Lower Control Flow Up backend:AMDGPU
#159557 opened Sep 18, 2025 by linuxrocks123 Loading… updated Nov 21, 2025
[AMDGPU] siloadstoreopt generate REG_SEQUENCE with aligned operands backend:AMDGPU
#162088 opened Oct 6, 2025 by JanekvO Loading… updated Nov 21, 2025
[AMDGPU] Implement codegen for GFX11+ V_CVT_PK_[IU]16_F32 backend:AMDGPU
#168719 opened Nov 19, 2025 by jayfoad Loading… updated Nov 21, 2025
[NFC][TTI] Introduce getInstructionUniformity API for uniformity analysis backend:AMDGPU backend:NVPTX llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen
#168903 opened Nov 20, 2025 by PankajDwivedi-25 Loading… updated Nov 21, 2025
[DAGCombiner] Honor rewrite semantics of fast-math flags in fdiv combine backend:AArch64 backend:AMDGPU backend:NVPTX backend:PowerPC backend:X86 floating-point Floating-point math llvm:SelectionDAG SelectionDAGISel as well
#167595 opened Nov 11, 2025 by mikolaj-pirog Loading… updated Nov 21, 2025
AMDGPU: Fix treating unknown mem operands as uniform backend:AMDGPU llvm:globalisel
#168980 opened Nov 21, 2025 by arsenm Loading… updated Nov 21, 2025
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned backend:AMDGPU
#160547 opened Sep 24, 2025 by JanekvO Loading… updated Nov 20, 2025
[TTI] Introduce getInstructionUniformity API for flexible uniformity analysis backend:AMDGPU backend:NVPTX llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen
#137639 opened Apr 28, 2025 by PankajDwivedi-25 Loading… updated Nov 20, 2025
[AMDGPU] Optimize rotate instruction selection patterns backend:AMDGPU llvm:globalisel
#143551 opened Jun 10, 2025 by aleksandar-amd Loading… updated Nov 20, 2025
[AMDGPU] [DO NOT MERGE] Nonsuccessful Attempt At Using SelectionDAG Hooks for abs i8/i16 backend:AMDGPU
#167064 opened Nov 8, 2025 by linuxrocks123 • Draft updated Nov 20, 2025
PHIElimination: add target hook to control reuse. backend:AMDGPU llvm:codegen llvm:regalloc
#163604 opened Oct 15, 2025 by jgu222 Loading… updated Nov 20, 2025
[AMDGPU] Disable dpp src1 sgpr on gfx11 backend:AMDGPU
#164241 opened Oct 20, 2025 by ptrojahn Loading… updated Nov 19, 2025
[AMDGPU][MC] Adding symbolic name for the constant 1 over 2*pi backend:AMDGPU llvm:globalisel mc
#160617 opened Sep 24, 2025 by jwanggit86 Loading… updated Nov 19, 2025
[AsmWriter] Fix MIR printing of single constant LLVM IR metadata backend:AMDGPU llvm:codegen llvm:globalisel llvm:ir
#165029 opened Oct 24, 2025 by saxlungs Loading… updated Nov 19, 2025
[AMDGPU] Use V_FMAC_F64 in "if (cond) a -= c" backend:AMDGPU llvm:globalisel
#168710 opened Nov 19, 2025 by vpykhtin Loading… updated Nov 19, 2025
[AMDGPU][True16][CodeGen] si-fix-sgpr-copies legalize size mismatched V2S copy with subreg case backend:AMDGPU
#161290 opened Sep 29, 2025 by broxigarchen • Draft updated Nov 18, 2025
[HLSL][SPIR-V] Implement vk::push_constant backend:AArch64 backend:AMDGPU backend:DirectX backend:SPIR-V backend:SystemZ backend:WebAssembly clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category HLSL HLSL Language Support
#166793 opened Nov 6, 2025 by Keenuts Loading… updated Nov 18, 2025
[AMDGPU] Initialize FrameOffsetReg for amdgpu_cs_chain functions backend:AMDGPU
#165518 opened Oct 29, 2025 by jofrn Loading… updated Nov 18, 2025
[InferAddressSpaces] Handle unconverted ptrmask backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#140802 opened May 20, 2025 by ro-i Loading… updated Nov 17, 2025
[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range backend:AMDGPU
#168358 opened Nov 17, 2025 by lucas-rami Loading… updated Nov 17, 2025
[DAGCombiner] Relax nsz constraint with fp->int->fp optimizations backend:AArch64 backend:AMDGPU backend:X86 floating-point Floating-point math llvm:SelectionDAG SelectionDAGISel as well
#164503 opened Oct 21, 2025 by guy-david Loading… updated Nov 17, 2025
[DAGCombiner] Relax nsz constraint for FP optimizations backend:AArch64 backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#165011 opened Oct 24, 2025 by guy-david Loading… updated Nov 17, 2025
[AMDGPU] Add intrinsic exposing s_alloc_vgpr backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir
#163951 opened Oct 17, 2025 by rovka Loading… updated Nov 17, 2025
AMDGPU: Select VGPR MFMAs by default backend:AMDGPU llvm:globalisel
#159493 opened Sep 18, 2025 by arsenm Loading… updated Nov 16, 2025
[mlir][amdgpu] Promote gpu.shuffle to amdgpu.dpp backend:AMDGPU mlir:gpu mlir
#155158 opened Aug 24, 2025 by tgymnich Loading… updated Nov 16, 2025
ProTip! What’s not been updated in a month: updated:<2025-11-01.