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Pull requests: llvm/llvm-project
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[TTI] Remove hasActiveVectorLength hook. NFC backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms vectorizers
#152977 opened Aug 11, 2025 by lukel97 Loading… updated Oct 22, 2025
[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size backend:RISC-V
#163501 opened Oct 15, 2025 by tclin914 Loading… updated Oct 26, 2025
[FPEnv][SDAG] Implement FNEARBYINT with optional chain backend:AArch64 backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#163081 opened Oct 12, 2025 by spavloff Loading… updated Oct 20, 2025
[clang][Driver] Support Outline Flags on RISC-V and X86 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#163664 opened Oct 16, 2025 by lenary Loading… updated Oct 16, 2025
[clang] Ensure -mno-outline adds attributes backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#163692 opened Oct 16, 2025 by lenary Loading… updated Oct 16, 2025
[SLP] Prefer copyable vectorization over alternate opcodes backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#153684 opened Aug 14, 2025 by alexey-bataev Loading… updated Oct 14, 2025
[SelectionDAG] Add SelectionDAGISel as well
f16 soft promotion for lrint and lround backend:AArch64 backend:ARM backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:SelectionDAG #152684 opened Aug 8, 2025 by tgross35 Loading… updated Oct 11, 2025
[libc][math][c++23] Add expbf16 math function backend:AMDGPU backend:RISC-V libc
#161919 opened Oct 3, 2025 by krishna2803 Loading… updated Oct 6, 2025
[DAG] Fold build_vector(build_pair()) patterns. backend:AMDGPU backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
[DAGCombiner] Set shift flags during visit. backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#91239 opened May 6, 2024 by goldsteinn • Draft updated Oct 2, 2025
[SelectionDAG] Use Magic Algorithm for Splitting UDIV/UREM by Constant backend:AArch64 backend:ARM backend:MIPS backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#154968 opened Aug 22, 2025 by mskamp Loading… updated Sep 29, 2025
[GlobalMerge] Convert GlobalMerge to a ModulePass backend:AArch64 backend:ARM backend:PowerPC backend:RISC-V llvm:codegen
#160703 opened Sep 25, 2025 by asb Loading… updated Sep 25, 2025
[DAGCombiner] Add pattern matching for negated subtraction in ABDU selection backend:AArch64 backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#156217 opened Aug 31, 2025 by AZero13 Loading… updated Sep 25, 2025
[RISCV][NFC] Refactor Vendor Reloc Declarations backend:RISC-V llvm:binary-utilities
#138226 opened May 2, 2025 by lenary Loading… updated Sep 24, 2025
[RISCV] Enable ShouldTrackLaneMasks when having vector instructions backend:RISC-V
#115843 opened Nov 12, 2024 by wangpc-pp Loading… updated Sep 22, 2025
[RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced backend:RISC-V
#159715 opened Sep 19, 2025 by ChunyuLiao Loading… updated Sep 22, 2025
[bolt][riscv] Fix conditional tail call backend:RISC-V BOLT
#160042 opened Sep 22, 2025 by zengdage Loading… updated Sep 22, 2025
Clang AST updates for more details backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category HLSL HLSL Language Support
#152372 opened Aug 6, 2025 by sei-nreimer Loading… updated Sep 18, 2025
[RISCV] Support for Zvabd fast-track proposal backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:mc Machine (object) code
#124239 opened Jan 24, 2025 by wangpc-pp Loading… updated Sep 18, 2025
Clang: Add nsz to llvm.minnum and llvm.maxnum emitted from fmin and fmax backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category floating-point Floating-point math llvm:ir
#113133 opened Oct 21, 2024 by wzssyqa Loading… updated Sep 14, 2025
[lldb] Implement RISCV function unwinding using instruction emulation backend:RISC-V lldb
#147434 opened Jul 8, 2025 by satyajanga • Draft updated Sep 12, 2025
[SLP] Check for extracts, being replaced by original scalars, for user nodes backend:RISC-V llvm:transforms vectorizers
#149572 opened Jul 18, 2025 by alexey-bataev Loading… updated Sep 11, 2025
[SLPVectorizer] Widen strided loads. backend:RISC-V llvm:transforms vectorizers
#153074 opened Aug 11, 2025 by mgudim Loading… updated Sep 11, 2025
[RISCV] Remove experimental from Zicfilp and Zicfiss backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#157015 opened Sep 5, 2025 by tclin914 Loading… updated Sep 10, 2025
ProTip! What’s not been updated in a month: updated:<2025-11-01.