- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#97995 by 4vtomat was merged Aug 31, 2024 Loading…
[RISCV][FMV] Support target_version backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#99040 by BeMg was merged Oct 4, 2024 Loading…
[RISCV][MC] Add support for Q extension backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:mc Machine (object) code
#139369 by el-ev was merged May 15, 2025 Loading…
[IVDesc] Unify RecurKinds [I|F]AnyOf backend:AArch64 backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#118393 by artagnon was merged May 23, 2025 Loading…
[RISCV] Support RISC-V Profiles in -march option backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:support
#76357 by wangpc-pp was merged Mar 22, 2024 Loading…
[llvm][RISCV] Support RISCV vector tuple type in llvm IR backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms
#97992 by 4vtomat was merged Aug 31, 2024 Loading…
[NFC] Rename IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category compiler-rt:sanitizer coroutines C++20 coroutines debuginfo llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms mlir:llvm mlir PGO Profile Guided Optimizations vectorizers
Intrinsic::getDeclaration to getOrInsertDeclaration backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 clang:codegen #111752 by jurahul was merged Oct 11, 2024 Loading…
Intrinsic: introduce minimumnum and maximumnum backend:AArch64 backend:loongarch backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category floating-point Floating-point math llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms vectorizers
#93841 by wzssyqa was merged Jun 21, 2024 Loading…
Switch builtin strings to use string tables backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#118734 by chandlerc was merged Dec 9, 2024 Loading…
[SelectionDAG][RISCV] Avoid store merging across function calls backend:RISC-V
#130430 by mikhailramalho was merged Mar 22, 2025 Loading…
[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. backend:RISC-V llvm:transforms vectorizers
#149042 by fhahn was merged Nov 12, 2025 Loading…
[TTI][RISCV]Improve costs for whole vector reg extract/insert. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#80164 by alexey-bataev was closed Mar 19, 2024 Loading…
[VPlan] Only use selectVectorizationFactor for cross-check (NFCI). backend:RISC-V llvm:transforms vectorizers
#103033 by fhahn was merged Aug 21, 2024 Loading…
[RISCV][CostModel] Add cost for fabs/fsqrt of type bf16/f16 backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#118608 by LiqinWeng was merged Jan 10, 2025 Loading…
[RISCV][CostModel] Updates reduction and shuffle cost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#77342 by arcbbb was merged Feb 29, 2024 Loading…
[RISCV][MachineCombiner] Add reassociation optimizations for RVV instructions backend:RISC-V
#88307 by mshockwave was merged Apr 25, 2024 Loading…
[Asan] Provide TTI hook to provide memory reference infromation of target intrinsics. backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#97070 by yetingk was merged Aug 8, 2024 Loading…
[AVR] Force relocations for non-encodable jumps backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:X86 llvm:mc Machine (object) code
#121498 by Patryk27 was merged Jan 20, 2025 Loading…
[RISCV] Implement EmitTargetCodeForMemset for Xqcilsm backend:RISC-V
#151555 by svs-quic was merged Aug 4, 2025 Loading…
[IA][RISCV] Recognize deinterleaved loads that could lower to strided segmented loads backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:codegen llvm:ir
#151612 by mshockwave was merged Aug 12, 2025 Loading…
Use Module level target-abi to assign target features for codegenerated functions. backend:RISC-V llvm:ir llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#100833 by hiraditya was closed Feb 27, 2025 Loading…
[Mips] Fix compiler crash when returning fp128 after calling a functi… backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:SelectionDAG SelectionDAGISel as well
#117525 by yingopq was merged Jan 20, 2025 Loading…
[Driver] Move CommonArgs to a location visible by the Frontend Drivers backend:AArch64 backend:AMDGPU backend:CSKY backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category flang:driver flang Flang issues not falling into any other category HLSL HLSL Language Support llvm:support
#142800 by mcinally was merged Jun 6, 2025 Loading…
[VPlan] Support VPWidenPointerInductionRecipes with EVL tail folding backend:RISC-V llvm:transforms vectorizers
#152110 by lukel97 was merged Aug 7, 2025 Loading…
[RISCV] Add XSfmm pseudo instruction and vset* insertion support backend:RISC-V
#143068 by 4vtomat was merged Oct 13, 2025 Loading…
ProTip! Updated in the last three days: updated:>2025-11-28.