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[mlir][AMDGPU] Add scaled wmma ops for gfx1250 backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169854 opened Nov 27, 2025 by justinrosner Loading…
[AMDGPU][InsertWaitCnts] Optimize loadcnt insertion at function boundaries backend:AMDGPU llvm:globalisel
#169647 opened Nov 26, 2025 by PankajDwivedi-25 Loading…
[AMDGPU] Fix Inefficient S_CSELECT_B64 Sequence backend:AMDGPU
#167780 opened Nov 12, 2025 by linuxrocks123 Loading…
[AMDGPU] Apply alignment attr for make.buffer.rsrc backend:AMDGPU clang Clang issues not falling into any other category llvm:transforms
#166914 opened Nov 7, 2025 by Shoreshen Loading…
AMDGPU: share LDS budget logic and add experimental LDS buffering pass backend:AMDGPU llvm:transforms
#166388 opened Nov 4, 2025 by yxsamliu Loading…
[AMDGPU] Match bitsin(typeof(x)) - popcnt(x) to s_bcnt0_i32 backend:AMDGPU clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir
#164847 opened Oct 23, 2025 by linuxrocks123 Loading…
PHIElimination: add target hook to control reuse. backend:AMDGPU llvm:codegen llvm:regalloc
#163604 opened Oct 15, 2025 by jgu222 Loading…
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading…
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses backend:AMDGPU llvm:globalisel
#162580 opened Oct 9, 2025 by doru1004 Loading…
[AMDGPU] Propagate alias information in AMDGPULowerKernelArguments. backend:AMDGPU
#161375 opened Sep 30, 2025 by PeddleSpam Loading…
[AMDGPU] Enable overwrite ALU bit in sched.barrier mask backend:AMDGPU
#160782 opened Sep 25, 2025 by jplehr Loading…
[AMDGPU][InstCombine] Fold ballot intrinsic based on llvm.assume hints backend:AMDGPU llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#160670 opened Sep 25, 2025 by TejaX-Alaghari Loading…
[AMDGPU] Emit b32 movs if (a)v_mov_b64_pseudo dest vgprs are misaligned backend:AMDGPU
#160547 opened Sep 24, 2025 by JanekvO Loading…
[AMDGPU]: Rewrite mbcnt_lo/mbcnt_hi to work item ID where applicable backend:AMDGPU llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#160496 opened Sep 24, 2025 by TejaX-Alaghari Loading…
[AMDGPU] Add sema check for global_atomic_fadd_v2f16 builtin backend:AMDGPU clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#158145 opened Sep 11, 2025 by tcgu-amd Loading…
[Verifier][AMDGPU] Restrict targets for chain calling convention. backend:AMDGPU llvm:ir
#157469 opened Sep 8, 2025 by jofrn Loading…
Try To Guess SGMasks for Inline Asm Instructions backend:AMDGPU
#155491 opened Aug 26, 2025 by linuxrocks123 Loading…
[AMDGPU] Post-RA AGPR copy elimination pass backend:AMDGPU
#153901 opened Aug 15, 2025 by lucas-rami • Draft
[AMDGPU] Add intrinsic-based optimization for rotate and funnel shift patterns backend:AMDGPU llvm:globalisel llvm:ir llvm:transforms
#153406 opened Aug 13, 2025 by aleksandar-amd Loading…
Limit Alloca->LDS promotion based on speculations as to eventual register pressure backend:AMDGPU
#152814 opened Aug 8, 2025 by linuxrocks123 Loading…
[X86] Remove LowerFCanonicalize and use generic expansion backend:AMDGPU backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#147877 opened Jul 10, 2025 by woruyu Loading…
IR/Verifier: Do not allow kernel to kernel calls. backend:AMDGPU llvm:ir
#144445 opened Jun 16, 2025 by jofrn Loading…
[Codegen] Remove redundant instruction using machinelateCleanup backend:AArch64 backend:AMDGPU backend:X86 llvm:codegen
#139716 opened May 13, 2025 by rohitaggarwal007 Loading…
[TTI] Introduce getInstructionUniformity API for flexible uniformity analysis backend:AMDGPU backend:NVPTX llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen
#137639 opened Apr 28, 2025 by PankajDwivedi-25 Loading…
AMDGPU: Allow operand folding between loop body and its preheader backend:AMDGPU
#137022 opened Apr 23, 2025 by akadutta Loading…
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