- Notifications
You must be signed in to change notification settings - Fork 15.4k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC backend:RISC-V
#170726 opened Dec 4, 2025 by topperc Loading…
[VPlan] Use nuw/nsw when computing {VF,VScale}xUF backend:RISC-V llvm:transforms vectorizers
#170710 opened Dec 4, 2025 by artagnon Loading…
[docs] [RISCV] Update docs regarding RV32E/RV64E backend:RISC-V
#170707 opened Dec 4, 2025 by RobinKastberg Loading…
[RISCV] Inserting indirect jumps with X7 for Zicfilp backend:RISC-V
#170683 opened Dec 4, 2025 by jaidTw Loading…
[RISCV] Update Zvqdotq to v0.1 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
#170648 opened Dec 4, 2025 by wangpc-pp Loading…
[RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa backend:RISC-V
#170612 opened Dec 4, 2025 by 4vtomat Loading…
[WIP][CodeGen] Allow register allocator to drive save/restore backend:RISC-V llvm:codegen
#170611 opened Dec 4, 2025 by ppenzin Loading…
[WIP][CodeGen] Enable early CFI backend:RISC-V llvm:codegen
#170610 opened Dec 4, 2025 by ppenzin Loading…
[WIP][CodeGen] Split
determineCalleeSaves backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:X86 backend:Xtensa llvm:codegen llvm:regalloc #170609 opened Dec 4, 2025 by ppenzin Loading…
[WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI backend:RISC-V debuginfo llvm:codegen llvm:mc Machine (object) code
#170607 opened Dec 4, 2025 by ppenzin Loading…
[WIP][CodeGen][RISCV] Allow multiple location for the same CSR. backend:RISC-V llvm:codegen
#170606 opened Dec 4, 2025 by ppenzin Loading…
[RISCV] improve SelectionDAGISel as well
musttail support backend:AArch64 backend:AMDGPU backend:RISC-V llvm:SelectionDAG #170547 opened Dec 3, 2025 by folkertdev Loading…
[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI backend:RISC-V
#170543 opened Dec 3, 2025 by lukel97 Loading…
[RISCV] Introduce new AND combine to expose additional load narrowing opportunities backend:RISC-V
#170483 opened Dec 3, 2025 by asb Loading…
[RISCV] Update P extension to the 018 version of the spec. backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
#170399 opened Dec 3, 2025 by topperc Loading…
[VPlan] Explicitly unoll replicate-regions without live-outs by VF. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170212 opened Dec 1, 2025 by fhahn Loading…
[LV][NFC] Remove unnecessary multiply in expandVPWidenIntOrFpInduction backend:RISC-V llvm:transforms vectorizers
#170159 opened Dec 1, 2025 by david-arm Loading…
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#170076 opened Dec 1, 2025 by rez5427 Loading…
[RISCV][llvm] Support PSLL codegen for P extension backend:RISC-V
#170074 opened Dec 1, 2025 by 4vtomat Loading…
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading…
[RISCV] LMUL lists for indexed and strided loads backend:RISC-V
#169756 opened Nov 27, 2025 by ppenzin Loading…
[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. backend:RISC-V
#169529 opened Nov 25, 2025 by topperc Loading…
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading…
Previous Next
ProTip! Type g i on any issue or pull request to go back to the issue listing page.