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Pull requests: llvm/llvm-project
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[DebugInfo][NVPTX] Adding support for Machine (object) code
inlined_at debug directive in NVPTX backend backend:NVPTX debuginfo llvm:codegen llvm:mc #170239 opened Dec 2, 2025 by laxmansole Loading…
Skip stack protectors on alloca's which have new metadata to opt out backend:AArch64 llvm:codegen
#170229 opened Dec 2, 2025 by cooperp Loading…
[RegAlloc] Remove redundant parameters for weightCalcHelper (NFC). llvm:codegen llvm:regalloc
#170151 opened Dec 1, 2025 by hstk30-hw Loading…
[MachineBasicBlock] Don't split loop header successor if the terminator is unanalyzable backend:NVPTX llvm:codegen
#170146 opened Dec 1, 2025 by XChy Loading…
[RegisterCoalescer] The COPY with the implicit-def of super register is not coalescable. backend:X86 llvm:codegen llvm:regalloc
#169997 opened Nov 29, 2025 by dianqk Loading…
[profcheck] Fix missing profile metadata in ExpandMemCmp llvm:codegen llvm:transforms
#169979 opened Nov 29, 2025 by jinhuang1102 Loading…
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading…
10 tasks
[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM backend:AMDGPU llvm:codegen llvm:regalloc
#169693 opened Nov 26, 2025 by PrasoonMishra Loading…
[WoA] Remove extra barriers after ARM LSE instructions with MSVC backend:AArch64 llvm:codegen
#169596 opened Nov 26, 2025 by UsmanNadeem Loading…
[AMDGPU] Insert inliner anchor earlier backend:AMDGPU llvm:codegen
#169478 opened Nov 25, 2025 by rovka Loading…
[X86] Remove redundant TEST after shifts when count is non-zero backend:X86 llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#169069 opened Nov 21, 2025 by GrumpyPigSkin Loading…
[LowerMemIntrinsics] Optimize memset lowering backend:AMDGPU backend:NVPTX backend:SPIR-V llvm:codegen llvm:globalisel llvm:transforms
#169040 opened Nov 21, 2025 by ritter-x2a Loading…
[RegisterCoalescer] Don't commute two-address instructions which only define a subregister backend:SystemZ backend:X86 llvm:codegen llvm:regalloc
#169031 opened Nov 21, 2025 by KRM7 Loading…
[NFC][TTI] Introduce getInstructionUniformity API for uniformity analysis backend:AMDGPU backend:NVPTX llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen
#168903 opened Nov 20, 2025 by PankajDwivedi-25 Loading…
[CFIInserter] Improve
CSRSavedLocation struct. llvm:codegen #168869 opened Nov 20, 2025 by mgudim Loading…
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading…
[CodeGen] Check physical def kill flag in MachineInstr::isDead backend:RISC-V llvm:codegen
#168684 opened Nov 19, 2025 by lukel97 Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveRegMatrix. backend:AMDGPU llvm:codegen llvm:regalloc
#168556 opened Nov 18, 2025 by vpykhtin Loading…
[regalloc][LiveRegMatrix] Add validity check for LiveRegMatrix to prevent dangling pointers llvm:codegen llvm:regalloc
#168553 opened Nov 18, 2025 by vpykhtin Loading…
[MTE] Add an attribute to opt-in memory tagging of global variables while using fsanitize=memtag-globals (#166380) clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:codegen
#168535 opened Nov 18, 2025 by tarcisiofischer Loading…
[CodeGen] Allow multiple location for the same CSR. backend:RISC-V llvm:codegen
#168531 opened Nov 18, 2025 by mgudim Loading…
[GlobalISel] Use ComputeValueTypes to implement computeValueLLTs (NFC) llvm:codegen
#168172 opened Nov 15, 2025 by s-barannikov Loading…
[InterleavedAccess] Construct interleaved access store with shuffles backend:AArch64 llvm:codegen llvm:transforms
#167737 opened Nov 12, 2025 by ram-NK Loading…
Adding Matching and Inference Functionality to Propeller-PR4: Implement matching and inference and create clusters backend:X86 llvm:codegen llvm:transforms PGO Profile Guided Optimizations
#167622 opened Nov 12, 2025 by wdx727 Loading…
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