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Pull requests: llvm/llvm-project
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Reapply inline spiller subranges backend:AMDGPU backend:X86 llvm:regalloc
#70194 opened Oct 25, 2023 by arsenm Loading…
[RegisterCoalescer] Skip CR_Replace pattern that has early-clobber in segment's edge llvm:codegen llvm:regalloc
#71024 opened Nov 2, 2023 by BeMg Loading…
[AArch64][GlobalISel] Basic SVE and fadd backend:AArch64 backend:AMDGPU llvm:globalisel llvm:regalloc
#72976 opened Nov 21, 2023 by davemgreen Loading…
[RegisterCoalescer] Fix reuse of instruction pointers llvm:regalloc
#73519 opened Nov 27, 2023 by vvuksanovic Loading…
[RISCV] Rematerialize load backend:RISC-V llvm:regalloc
#73924 opened Nov 30, 2023 by niwinanto Loading…
[LiveDebugVariables] Add basic verification debuginfo llvm:regalloc
#79846 opened Jan 29, 2024 by jayfoad Loading…
[MCP] Move dependencies if they block copy propagation backend:AArch64 backend:ARM backend:X86 llvm:globalisel llvm:regalloc
#105562 opened Aug 21, 2024 by spaits Loading…
[AMDGPU] Change CF intrinsics lowering to reconverge on predecessors backend:AMDGPU clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:ir llvm:regalloc
#108596 opened Sep 13, 2024 by alex-t Loading…
[NFC] Add
const for readability backend:RISC-V llvm:regalloc llvm:transforms vectorizers #116611 opened Nov 18, 2024 by pfusik Loading…
[CodeGen] Introduce MI flag for Live Range split instructions llvm:codegen llvm:regalloc
#117543 opened Nov 25, 2024 by cdevadas Loading…
[TRI] Remove reserved registers in getRegPressureSetLimit backend:AMDGPU backend:ARM backend:loongarch backend:NVPTX backend:PowerPC backend:X86 llvm:globalisel llvm:regalloc llvm:transforms tablegen
#118787 opened Dec 5, 2024 by wangpc-pp Loading…
[CodeGen][Spill2Reg] Initial patch backend:X86 llvm:regalloc llvm:transforms
#118832 opened Dec 5, 2024 by vporpo Loading…
CodeGen: Treat subreg-to-subreg copies as isFullCopyInstr backend:AMDGPU llvm:regalloc
#120056 opened Dec 16, 2024 by arsenm Loading…
RegAllocGreedy: Fix subrange based instruction split logic backend:AMDGPU llvm:regalloc
#120199 opened Dec 17, 2024 by arsenm Loading…
[TableGen][GISel] Create untyped registers during instruction selection backend:AMDGPU llvm:globalisel llvm:regalloc tablegen
#121270 opened Dec 28, 2024 by s-barannikov Loading…
[AMDGPU][NPM] Support -regalloc-npm options backend:AMDGPU llvm:regalloc
#129035 opened Feb 27, 2025 by optimisan Loading…
[RegisterCoalescer]: Try inflated RC for coalescing backend:AMDGPU backend:PowerPC llvm:regalloc
#130870 opened Mar 12, 2025 by jrbyrnes Loading…
Address Codegen bug related to marking subregister MachineOperand defines as undef backend:AMDGPU llvm:regalloc
#134929 opened Apr 8, 2025 by bababuck Loading…
[SystemZ] Add a SystemZ specific pre-RA scheduling strategy. backend:SystemZ llvm:codegen llvm:regalloc
#135076 opened Apr 9, 2025 by JonPsson1 Loading…
Revert "[InlineSpiller] Check rematerialization before folding operand (#134015)" backend:X86 llvm:regalloc
#137801 opened Apr 29, 2025 by arsenm Loading…
[CodeGen] Fix VNInfo mapping in LiveRange::assign llvm:regalloc
#148790 opened Jul 15, 2025 by pzzp Loading…
Fix SIFixSGPRCopies To Handle Physical Registers backend:AMDGPU llvm:codegen llvm:regalloc
#149859 opened Jul 21, 2025 by linuxrocks123 • Draft
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ProTip! Updated in the last three days: updated:>2025-11-28.