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Pull requests list

Avoid maxnum(sNaN, x) optimizations / folds backend:AMDGPU backend:ARM backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#170181 opened Dec 1, 2025 by LewisCrawford Loading…
5
[Arm] Control forced unrolling of small loops backend:ARM
#170127 opened Dec 1, 2025 by VladiKrapp-Arm Loading…
6
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading…
4
[ARM] Introduce intrinsics for MVE vcmp under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169798 opened Nov 27, 2025 by davemgreen Loading…
2
[ARM] Introduce intrinsics for MVE vrnd under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169797 opened Nov 27, 2025 by davemgreen Loading…
2
[ARM] Introduce intrinsics for MVE minnm/maxnm under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169795 opened Nov 27, 2025 by davemgreen Loading…
4
[AArch64][ARM] Optimize more tbl/tbx calls into shufflevector backend:AArch64 backend:ARM llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169748 opened Nov 26, 2025 by valadaptive Loading…
1
5
[AArch64][ARM] Move ARM-specific InstCombine transforms to new module backend:AArch64 backend:ARM llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169589 opened Nov 26, 2025 by valadaptive Loading…
9
Fixes inlining issue in armv7 backend:ARM llvm:transforms
#169337 opened Nov 24, 2025 by CrooseGit Loading…
11
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading…
12
release/21.x: [ARM] Use TargetMachine over Subtarget in ARMAsmPrinter (#166329) backend:ARM
#168380 opened Nov 17, 2025 by llvmbot Loading… LLVM 21.x Release
9
[ARM] Cleanup unused ARMbrcond. NFC backend:ARM
#168040 opened Nov 14, 2025 by davemgreen Loading…
2
DAG: Use poison for some load/store offsets in legalizer backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167756 opened Nov 12, 2025 by arsenm Loading…
2
[ARM] Add missing cases of SubsumesPredicate backend:ARM
#167524 opened Nov 11, 2025 by AZero13 Loading…
1
RuntimeLibcalls: Add entries for stack probe functions backend:AArch64 backend:ARM backend:X86 llvm:ir
#167453 opened Nov 11, 2025 by arsenm Loading…
10
[ConstantTime] Native ct.select support for ARM32 and Thumb backend:ARM
#166707 opened Nov 6, 2025 by wizardengineer Loading…
3
[SelectionDAG] Optimize BSWAP yet again once more backend:ARM llvm:SelectionDAG SelectionDAGISel as well
#165292 opened Oct 27, 2025 by AZero13 Loading…
12
[ARM] Only change mask if demanded bits says we can optimize backend:ARM
#165106 opened Oct 25, 2025 by AZero13 Loading…
5
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading…
10
Implement hasOrNot backend:AArch64 backend:ARM llvm:SelectionDAG SelectionDAGISel as well
#163995 opened Oct 17, 2025 by AZero13 Loading…
3
[ARM] Allow usubo and uaddo to happen for any legal type backend:AArch64 backend:ARM
#163457 opened Oct 14, 2025 by AZero13 Loading…
2
[ARM] Enable creation of ARMISD::CMN nodes backend:ARM
#163223 opened Oct 13, 2025 by AZero13 Loading…
4
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading…
32
[ARM] Use addc nodes when lowering overflow backend:ARM
#162583 opened Oct 9, 2025 by AZero13 Loading…
3
cmse: emit __acle_se_ symbol for aliases to entry functions backend:ARM
#162109 opened Oct 6, 2025 by folkertdev Loading…
1
4
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