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Reland "[LICM] Sink unused l-invariant loads in preheader #157559" backend:AMDGPU backend:PowerPC llvm:transforms
#170204 opened Dec 1, 2025 by VigneshwarJ Loading…
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading…
10 tasks
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading…
[PowerPC] cost modeling for length type VP intrinsic load/store backend:PowerPC llvm:analysis Includes value tracking, cost tables and constant folding
#168938 opened Nov 20, 2025 by RolandF77 Loading…
[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading…
[PowerPC] Add AMO load signed builtins backend:PowerPC backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#168747 opened Nov 19, 2025 by maryammo Loading…
[PowerPC] Add initial support for AMO load builtins backend:PowerPC backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category llvm:ir
#168746 opened Nov 19, 2025 by maryammo Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
[DAGCombiner] Honor rewrite semantics of fast-math flags in fdiv combine backend:AArch64 backend:AMDGPU backend:NVPTX backend:PowerPC backend:X86 floating-point Floating-point math llvm:SelectionDAG SelectionDAGISel as well
#167595 opened Nov 11, 2025 by mikolaj-pirog Loading…
[InferAlignment] Enhance alignment propagation for and(ptrtoint, const) pattern. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ clang Clang issues not falling into any other category coroutines C++20 coroutines llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#166935 opened Nov 7, 2025 by egorshamshura Loading…
[PowerPC] Use the same lowering rule for vector rounding instructions backend:PowerPC
#166307 opened Nov 4, 2025 by paperchalice Loading…
[PowerPC][MC] Diagnose out of range branch fixups backend:PowerPC
#165859 opened Oct 31, 2025 by nikic Loading…
[PowerPC] Add xor-not patterns to eqv backend:PowerPC
#165043 opened Oct 24, 2025 by AZero13 Loading…
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading…
[FPEnv][SDAG] Implement FNEARBYINT with optional chain backend:AArch64 backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#163081 opened Oct 12, 2025 by spavloff Loading…
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading…
[PowerPC] Remove NoInfsFPMath uses backend:PowerPC
#163029 opened Oct 12, 2025 by paperchalice Loading…
Fix spelling of 'auxiliary' in XCOFF and related docs backend:PowerPC lldb llvm:binary-utilities llvm:ir llvm:mc Machine (object) code
#162956 opened Oct 11, 2025 by smallzhong Loading…
[PowerPC] support tail call optimization on AIX tail call backend:PowerPC
#161690 opened Oct 2, 2025 by diggerlin Loading…
[GlobalMerge] Convert GlobalMerge to a ModulePass backend:AArch64 backend:ARM backend:PowerPC backend:RISC-V llvm:codegen
#160703 opened Sep 25, 2025 by asb Loading…
[IR] Allow fast math flags on fptosi, fptoui and sitofp backend:AMDGPU backend:PowerPC clang Clang issues not falling into any other category floating-point Floating-point math HLSL HLSL Language Support llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms
#160475 opened Sep 24, 2025 by paperchalice Loading…
CodeGen: Introduce MachineFunction::getPreferredAlignment(). backend:PowerPC backend:X86 llvm:codegen
#158368 opened Sep 12, 2025 by pcc Loading…
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading…
[SCEV] Add initial support for ptrtoaddr. backend:PowerPC llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms
#158032 opened Sep 11, 2025 by fhahn Loading…
[DAGCombiner] Add pattern matching for negated subtraction in ABDU selection backend:AArch64 backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#156217 opened Aug 31, 2025 by AZero13 Loading…
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