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Pull requests list

[SPIRV] Use AMDGPU ABI for AMDGCN flavoured SPIRV backend:AMDGPU backend:SPIR-V clang:codegen IR generation bugs: mangling, exceptions, etc.
#169865 opened Nov 28, 2025 by AlexVlx Loading…
9
[SPIRV] Error for zero-length arrays if not a shader backend:SPIR-V
#169732 opened Nov 26, 2025 by sarnex Loading…
4
[SPIR-V] Move ASSIGN_TYPE generation to PostLegalizer backend:SPIR-V
#169696 opened Nov 26, 2025 by s-perron Loading…
5
[SPIRV] Add legalization for long vectors backend:SPIR-V llvm:globalisel
#169665 opened Nov 26, 2025 by s-perron Loading…
15
[SPIRV] Addition of extension SPV_KHR_non_semantic_info and SPV_KHR_relaxed_extended_instruction backend:SPIR-V
#169643 opened Nov 26, 2025 by aadeshps-mcw Loading…
3
[SPIRV] Add support for pointers to functions with aggregate args/returns as global variables / constant initialisers backend:SPIR-V
#169595 opened Nov 26, 2025 by AlexVlx Loading…
16
[clang][Driver][SPIR-V] Allow linking IR using llvm-link backend:SPIR-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#169572 opened Nov 25, 2025 by sarnex Loading…
5
[HLSL][SPIR-V] Implement vk::location for inputs backend:SPIR-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" HLSL HLSL Language Support
#169479 opened Nov 25, 2025 by Keenuts Loading…
10
[SPIR-V] [HLSL] Add CheckAccessFullyMapped HLSL function. backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
#169398 opened Nov 24, 2025 by bob80905 • Draft
1
2
[LowerMemIntrinsics] Optimize memset lowering backend:AMDGPU backend:NVPTX backend:SPIR-V llvm:codegen llvm:globalisel llvm:transforms
#169040 opened Nov 21, 2025 by ritter-x2a Loading…
6
[HLSL] Implement ddx and ddy HLSL intrinsics backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
#168887 opened Nov 20, 2025 by Alexander-Johnston Loading…
2
3
[HLSL] Implement ddx/ddy_fine intrinsics backend:DirectX backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics HLSL HLSL Language Support llvm:ir
#168874 opened Nov 20, 2025 by Alexander-Johnston Loading…
2
6
[HLSL][SPIR-V] Add support for SV_Target semantic backend:SPIR-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" HLSL HLSL Language Support
#168743 opened Nov 19, 2025 by Keenuts Loading…
11
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
21
[SPIRV] Add support for CodeSectionINTEL storage class in legalizer backend:SPIR-V llvm:globalisel
#167961 opened Nov 13, 2025 by sarnex Loading…
24
[HLSL][DXIL][SPIRV] WavePrefixSum intrinsic support backend:DirectX backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category HLSL HLSL Language Support llvm:ir
#167946 opened Nov 13, 2025 by kcloudy0717 Loading…
12 tasks done
11
[HLSL][SPIR-V] Implement vk::push_constant backend:AArch64 backend:AMDGPU backend:DirectX backend:SPIR-V backend:SystemZ backend:WebAssembly clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category HLSL HLSL Language Support
#166793 opened Nov 6, 2025 by Keenuts Loading…
15
[SPIR-V] Enable structurizer for kernel environment backend:SPIR-V
#166079 opened Nov 2, 2025 by MrSidims • Draft
9
[CodeGen][PreISelIntrinsicLowering] Add VP-based lowering for memcpy/memmove/memset backend:NVPTX backend:RISC-V backend:SPIR-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#165585 opened Oct 29, 2025 by dadra-oc Loading…
16
[HLSL][DXIL][SPIRV] Added WaveActiveBitOr HLSL intrinsic backend:DirectX backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category HLSL HLSL Language Support llvm:ir
#165156 opened Oct 26, 2025 by KungFuDonkey Loading…
12 tasks done
35
[HLSL][DXIL][SPRIV] Added WaveActiveProduct intrinsic #164385 backend:DirectX backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category HLSL HLSL Language Support llvm:ir
#165109 opened Oct 25, 2025 by KungFuDonkey Loading…
12 tasks done
10
[SPIRV] Add shadow function when only global variable declared in the module backend:SPIR-V
#164829 opened Oct 23, 2025 by YixingZhang007 • Draft
2
[RFC][SPIR-V] Add intrinsics to convert to/from ap.float backend:SPIR-V llvm:globalisel llvm:ir
#164252 opened Oct 20, 2025 by MrSidims Loading…
61
[SPIRV] fix alloca -> OpVariable lowering backend:SPIR-V
#164175 opened Oct 19, 2025 by simeonschaub Loading…
1
3
[SPIRV] Add support for arbitrary-precision integers larger than 64 bits in SPIR-V backend backend:SPIR-V
#161270 opened Sep 29, 2025 by YixingZhang007 • Draft
3
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