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Pull requests: llvm/llvm-project
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[AMDGPU] Apply alignment attr for make.buffer.rsrc backend:AMDGPU clang Clang issues not falling into any other category llvm:transforms
#166914 opened Nov 7, 2025 by Shoreshen Loading… updated Dec 2, 2025
[AMDGPU] Generate waterfall for calls with SGPR(inreg) argument backend:AMDGPU
#146997 opened Jul 4, 2025 by Shoreshen Loading… updated Dec 2, 2025
[mlir][AMDGPU] Add scaled wmma ops for gfx1250 backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169854 opened Nov 27, 2025 by justinrosner Loading… updated Dec 2, 2025
VectorCombine: Fold chains of shuffles fed by length-changing shuffles backend:AMDGPU llvm:transforms llvm:vectorcombine vectorizers
#168819 opened Nov 20, 2025 by nhaehnle Loading… updated Dec 1, 2025
[AMDGPU] Reland "Remove leftover implicit operands from SI_SPILL/SI_RESTORE" backend:AMDGPU
#169449 opened Nov 25, 2025 by LU-JOHN Loading… updated Dec 1, 2025
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
[DAG] Use known-bits when creating umulh/smulh. backend:AMDGPU backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#160916 opened Sep 26, 2025 by davemgreen Loading… updated Dec 1, 2025
[mlir][amdgpu] Add lowering for make_dma_descriptor backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169955 opened Nov 28, 2025 by amd-eochoalo Loading… updated Dec 1, 2025
[IR] Add CallBr intrinsics support backend:AMDGPU llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms
#133907 opened Apr 1, 2025 by ro-i Loading… updated Dec 1, 2025
[AMDGPU] Propagate debug locations to compiler-generated instructions backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
#168573 opened Nov 18, 2025 by aleksandar-amd Loading… updated Dec 1, 2025
[AMDGPU] Rematerialize VGPR candidates when SGPR spills results in VGPR Excess backend:AMDGPU
#168079 opened Nov 14, 2025 by jmmartinez Loading… updated Dec 1, 2025
[AMDGPU] Verify dominance when rewriting spills to registers backend:AMDGPU
#167347 opened Nov 10, 2025 by kerbowa Loading… updated Dec 1, 2025
[AMDGPU][SIInsertWaitCnts] Use RegUnits-based tracking backend:AMDGPU
#162077 opened Oct 6, 2025 by Pierre-vh Loading… updated Nov 28, 2025
[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) backend:AArch64 backend:AMDGPU llvm:codegen llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well tablegen
#155107 opened Aug 23, 2025 by DenisGZM Loading… updated Nov 28, 2025
[AMDGPU] Allow negative offsets in scratch instructions backend:AMDGPU llvm:codegen llvm:globalisel
#166979 opened Nov 7, 2025 by gandhi56 Loading… updated Nov 27, 2025
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading… updated Nov 27, 2025
[AMDGPU] Register allocation anti-hints to reduce MFMA hazard NOPs backend:AMDGPU
#156943 opened Sep 4, 2025 by mssefat Loading… updated Nov 27, 2025
[AMDGPU][InsertWaitCnts] Optimize loadcnt insertion at function boundaries backend:AMDGPU llvm:globalisel
#169647 opened Nov 26, 2025 by PankajDwivedi-25 Loading… updated Nov 27, 2025
[LowerMemIntrinsics] Optimize memset lowering backend:AMDGPU backend:NVPTX backend:SPIR-V llvm:codegen llvm:globalisel llvm:transforms
#169040 opened Nov 21, 2025 by ritter-x2a Loading… updated Nov 26, 2025
[AMDGPU] Update log lowering to remove contract for AMDGCN backend backend:AMDGPU
#168916 opened Nov 20, 2025 by adelejjeh Loading… updated Nov 26, 2025
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses backend:AMDGPU llvm:globalisel
#162580 opened Oct 9, 2025 by doru1004 Loading… updated Nov 26, 2025
[AMDGPU] IGLP: Fix static variables backend:AMDGPU
#137549 opened Apr 27, 2025 by ro-i Loading… updated Nov 26, 2025
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading… updated Nov 26, 2025
[AMDGPU] Implement CFI for CSR spills backend:AMDGPU llvm:globalisel
#164724 opened Oct 22, 2025 by slinder1 Loading… updated Nov 25, 2025
Use register pair for PC spill backend:AMDGPU llvm:globalisel
#169098 opened Nov 21, 2025 by slinder1 Loading… updated Nov 25, 2025
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ProTip! Updated in the last three days: updated:>2025-11-28.