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Revert "[RegAlloc] Relax the split constrain on MBB prolog" backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#169990 by ronlieb was merged Nov 29, 2025 Loading…
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading…
AMDGPU: Stop implementing shouldCoalesce backend:AMDGPU llvm:globalisel llvm:regalloc
#168988 by arsenm was merged Nov 21, 2025 Loading…
[RegAlloc] Relax the split constrain on MBB prolog backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#168259 by LuoYuanke was merged Nov 28, 2025 Loading…
RenameIndependentSubregs: try to only implicit def used subregs backend:AMDGPU llvm:codegen llvm:globalisel llvm:regalloc
#167486 by perlfu was merged Nov 20, 2025 Loading…
Remove unused standard header inclusion: <iterator>, <utility>, <type_traits> backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:RISC-V backend:SPIR-V backend:SystemZ backend:X86 debuginfo llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:binary-utilities llvm:codegen llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:mc Machine (object) code llvm:regalloc llvm:support llvm:transforms PGO Profile Guided Optimizations platform:windows tablegen tools:llvm-exegesis xray
#167318 by serge-sans-paille was closed Nov 11, 2025 Loading…
AMDGPU: Relax shouldCoalesce to allow more register tuple widening backend:AMDGPU llvm:globalisel llvm:regalloc
#166475 by arsenm was merged Nov 11, 2025 Loading…
Hexagon: Enable terminal rule backend:Hexagon llvm:regalloc
#165960 by arsenm was merged Nov 11, 2025 Loading…
ARM: Enable terminal rule backend:ARM llvm:regalloc
#165958 by arsenm was merged Nov 10, 2025 Loading…
[RegAlloc] Constrain rematted regclass to use backend:AArch64 llvm:codegen llvm:regalloc
#164386 by lukel97 was merged Oct 23, 2025 Loading…
[NFC][LLVM][CodeGen] Namespace related cleanups backend:PowerPC llvm:codegen llvm:regalloc mlgo
#162999 by jurahul was merged Oct 13, 2025 Loading…
RegisterCoalescer: Avoid return after else llvm:codegen llvm:regalloc
#161622 by arsenm was merged Oct 2, 2025 Loading…
RegisterCoalescer: Enable terminal rule by default for AMDGPU backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc llvm:transforms
#161621 by arsenm was merged Nov 10, 2025 Loading…
[RegAlloc] Account for use availability when applying rematerializable weight discount backend:AMDGPU backend:RISC-V llvm:codegen llvm:regalloc
#159180 by lukel97 was merged Sep 25, 2025 Loading…
CodeGen: Remove TRI arguments from stack load/store hooks backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG SelectionDAGISel as well tablegen
#158240 by arsenm was merged Nov 11, 2025 Loading…
[LiveRegUnits] Exclude runtime defined liveins when computing liveouts backend:AArch64 llvm:codegen llvm:regalloc
#154325 by MacDue was merged Aug 21, 2025 Loading…
[CodeGen] Prevent register coalescer rematerialization based on target backend:AArch64 llvm:codegen llvm:regalloc
#148430 by tomershafir was closed Jul 24, 2025 Loading…
[CodeGen][NPM] Port ProcessImplicitDefs to NPM backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#148110 by vikramRH was merged Jul 16, 2025 Loading…
[CodeGen] Prevent register coalescer rematerialization for zero cycle regmoves backend:AArch64 llvm:codegen llvm:regalloc
#147571 by tomershafir was closed Jul 10, 2025 Loading…
[TII] Do not fold undef copies backend:AMDGPU llvm:codegen llvm:regalloc
#147392 by jrbyrnes was merged Jul 17, 2025 Loading…
[MCP] Handle iterative simplification during forward copy prop llvm:globalisel llvm:regalloc
#140267 by preames was merged Jun 2, 2025 Loading…
[LLVM][CodeGen] Add convenience accessors for MachineFunctionProperties debuginfo llvm:globalisel llvm:regalloc llvm:SelectionDAG SelectionDAGISel as well
#140002 by jurahul was merged May 22, 2025 Loading…
[CodeGen][NPM] Port ProcessImplicitDefs to NPM backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#138829 by optimisan was closed Jul 11, 2025 Loading…
[RISCV][TII] Add and use new hook to optimize/canonicalize instructions after MachineCopyPropagation backend:RISC-V llvm:regalloc
#137973 by asb was merged May 8, 2025 Loading…
[X86][BreakFalseDeps] Using reverse order for undef register selection backend:X86 llvm:codegen llvm:regalloc tablegen
#137569 by phoebewang was merged Jun 11, 2025 Loading…
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