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[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#169890 by arcbbb was merged Nov 30, 2025 Loading…
[VPlan] Optimize LastActiveLane to EVL - 1 backend:RISC-V llvm:transforms vectorizers
#169766 by lukel97 was merged Nov 27, 2025 Loading…
[MC][RISCV] Add missing Predicates for NDS_FMV_BF16_X backend:RISC-V
#169662 by sunshaoce was merged Nov 26, 2025 Loading…
Revert [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#169653 by daniilavdeev was merged Nov 26, 2025 Loading…
[RISCV] Use FMV.D for moving GPRPairs on RV32_Zdinx backend:RISC-V
#169556 by lenary was merged Nov 25, 2025 Loading…
[RISCV] Don't add duplicate Zilsd hints. backend:RISC-V
#169554 by topperc was merged Nov 26, 2025 Loading…
[RISCV] Don't add Zilsd pairing hints if part of the pair is reserved. backend:RISC-V
#169538 by topperc was merged Nov 25, 2025 Loading…
[VPlan] Include flags in VectorPointerRecipe::printRecipe backend:RISC-V llvm:transforms vectorizers
#169466 by artagnon was merged Nov 25, 2025 Loading…
[RISCV] Add assertions to VSETVLIInfo accessors. NFC backend:RISC-V
#169462 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Propagate SDNode flags when combining
(fmul (fneg X), ...) backend:RISC-V #169460 by mshockwave was merged Nov 25, 2025 Loading…
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. backend:RISC-V
#169459 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Initialize AltFmt and TWiden in the VSETVLIInfo default constructor. backend:RISC-V
#169457 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Use an enum class for AVL state ins RISCVInsertVSETVLI. NFC backend:RISC-V
#169455 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Use a switch in VSETVLIInfo::print(). NFC backend:RISC-V
#169441 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Add a InstRW to COPY in RISCVSchedSpacemitX60.td. backend:RISC-V
#169423 by topperc was merged Nov 25, 2025 Loading…
[VPlan] Use DL index type consistently for GEPs backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#169396 by artagnon was merged Nov 26, 2025 Loading…
[VPlan] Handle scalar VPWidenPointerInd in convertToConcreteRecipes. backend:RISC-V llvm:transforms vectorizers
#169338 by fhahn was merged Nov 27, 2025 Loading…
[LLD] Add support for statically resolved vendor-specific RISCV relocations. backend:RISC-V lld:ELF lld
#169273 by resistor was merged Nov 28, 2025 Loading…
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading…
[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. backend:RISC-V
#169182 by topperc was merged Nov 23, 2025 Loading…
[llvm][RISCV] Handle atomic and volatile in ZilsdOptimizer backend:RISC-V
#169169 by 4vtomat was closed Nov 22, 2025 Loading…
[RISCV][llvm] Support BUILD_VECTOR codegen for P extension backend:RISC-V
#169083 by 4vtomat was merged Nov 26, 2025 Loading…
[RISCV] Remove custom isel lowering of i64 to Zilsd load/store. backend:RISC-V
#169067 by topperc was closed Nov 25, 2025 Loading…
[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit truncation exists backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169022 by XChy was merged Nov 21, 2025 Loading…
[RISCV] Combine vslide{up,down} x, poison -> x backend:RISC-V
#169013 by lukel97 was merged Nov 24, 2025 Loading…
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