Skip to content

Pull requests: llvm/llvm-project

New pull request New
Clear current search query, filters, and sorts
179 Open 1,830 Closed
179 Open 1,830 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[AMDGPU] Change the immediate operand of s_waitcnt_depctr / s_wait_alu backend:AMDGPU llvm:globalisel
#169378 by jayfoad was merged Nov 25, 2025 Loading…
19
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading…
2
[TableGen] Constify CodeGenInstruction where possible (NFC) llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well tablegen
#169193 by s-barannikov was merged Nov 23, 2025 Loading…
2
[TableGen] Use MVT instead of MVT::SimpleValueType. NFC llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well tablegen
#169180 by topperc was merged Nov 23, 2025 Loading…
6
[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) backend:AMDGPU llvm:globalisel
#169016 by cdevadas was merged Nov 21, 2025 Loading…
5
AMDGPU: Stop implementing shouldCoalesce backend:AMDGPU llvm:globalisel llvm:regalloc
#168988 by arsenm was merged Nov 21, 2025 Loading…
3
[AArch64][GlobalISel] Check unmergeSrc is a vector in matchCombineBuildUnmerge backend:AArch64 llvm:globalisel
#168692 by HolyMolyCowMan was merged Nov 19, 2025 Loading…
1
12
[RegAlloc] Fix the terminal rule check for interfere with DstReg backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168661 by hstk30-hw was merged Nov 23, 2025 Loading…
35
[GISel] Use getScalarSizeInBits in LegalizerHelper::lowerBitCount llvm:globalisel
#168584 by topperc was merged Nov 18, 2025 Loading…
22
[GISel][RISCV] Compute CTPOP of small odd-sized integer correctly backend:RISC-V llvm:globalisel
#168559 by XChy was merged Nov 18, 2025 Loading…
9
[X86][GISel] Fix crash on bitcasting i16 <-> half with gisel enabled. backend:X86 llvm:globalisel
#168456 by GrumpyPigSkin was merged Nov 25, 2025 Loading…
1
27
[AArch64][GlobalISel] Add better basic legalization for llround. backend:AArch64 llvm:globalisel
#168427 by davemgreen was merged Nov 18, 2025 Loading…
5
AMDGPU/GlobalISel: RegBankLegalize rules for G_FABS and G_FNEG backend:AMDGPU llvm:globalisel
#168411 by petar-avramovic was merged Nov 24, 2025 Loading…
12
AMDGPU/GlobalISel: Combine S16 copy-trunc-readanylane-anyext backend:AMDGPU llvm:globalisel
#168410 by petar-avramovic was merged Nov 24, 2025 Loading…
6
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:loongarch backend:PowerPC backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168353 by sdesmalen-arm was merged Nov 24, 2025 Loading…
26
[DAG] Add strictfp implicit def reg after metadata. backend:AArch64 backend:AMDGPU backend:ARM backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#168282 by davemgreen was merged Nov 17, 2025 Loading…
1
3
Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain backend:AMDGPU llvm:globalisel llvm:transforms vectorizers
#168135 by cmc-rep was merged Nov 20, 2025 Loading…
29
Revert "[Transform][LoadStoreVectorizer] allow redundant in Chain (#1… backend:AMDGPU llvm:globalisel llvm:transforms vectorizers
#168105 by cmc-rep was merged Nov 14, 2025 Loading…
4
[AArch64][GISel] Don't crash in known-bits when copying from vectors to non-vectors backend:AArch64 llvm:globalisel
#168081 by cofibrant was merged Nov 18, 2025 Loading…
1
9
Cleanups in AArch64 backend:AArch64 backend:X86 llvm:globalisel
#168025 by echristo was merged Nov 15, 2025 Loading…
3
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL backend:AMDGPU llvm:globalisel
#167847 by vangthao95 was merged Nov 17, 2025 Loading…
2
[RISCV][GISel] Fallback to SelectionDAG for vleff intrinsics. backend:RISC-V llvm:globalisel
#167776 by topperc was merged Nov 13, 2025 Loading…
1
4
[NFC][SPIRV][IRTranslator] Replace leftover MF->getTarget().getTargetTriple().isSPIRV() with targetSupportsBF16Type(MF) llvm:globalisel
#167704 by jmmartinez was merged Nov 12, 2025 Loading…
@jmmartinez
2
[AMDGPU] Insert s_wait_xcnt(0) before atomics to work around write combining misses hazards backend:AMDGPU llvm:globalisel
#167605 by shiltian was closed Nov 13, 2025 Loading…
10
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_IS_FPCLASS backend:AMDGPU llvm:globalisel
#167575 by vangthao95 was merged Nov 18, 2025 Loading…
3
ProTip! Exclude everything labeled bug with -label:bug.