- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[ARM] Disable strict node mutation and use correct lowering for several strict ops backend:ARM
#170136 by Varnike was merged Dec 1, 2025 Loading…
[ARM] Introduce intrinsics for MVE fma under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169771 by davemgreen was merged Nov 30, 2025 Loading…
[ARM] Introduce intrinsics for MVE add/sub/mul under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169156 by davemgreen was merged Nov 25, 2025 Loading…
[ARM] Restore hasSideEffects flag on t2WhileLoopSetup backend:ARM
#168948 by s-barannikov was merged Nov 21, 2025 Loading…
CodeGen: Move libcall lowering configuration to subtarget backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168621 by arsenm was merged Nov 25, 2025 Loading…
CodeGen: Add subtarget to TargetLoweringBase constructor backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168620 by arsenm was merged Nov 19, 2025 Loading…
[DAG] Add strictfp implicit def reg after metadata. backend:AArch64 backend:AMDGPU backend:ARM backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#168282 by davemgreen was merged Nov 17, 2025 Loading…
[ARM] Remove Subtarget from ARMAsmPrinter backend:ARM
#168264 by davemgreen was merged Nov 27, 2025 Loading…
[GlobalMerge] add a command to force global merge backend:ARM llvm:codegen
#168231 by Zhenhang1213 was closed Nov 20, 2025 Loading…
[revert][CodeGen] add a command to force global merge backend:ARM llvm:codegen
#168230 by Zhenhang1213 was merged Nov 15, 2025 Loading…
[ARM] TableGen-erate node descriptions backend:ARM
#168212 by s-barannikov was merged Nov 18, 2025 Loading…
[ARM] Pattern match Low Overhead Loops pseudos (NFC) backend:ARM
#168209 by s-barannikov was merged Nov 18, 2025 Loading…
[Clang][Sema] Emit diagnostic for __builtin_vectorelements(<SVEType>) when SVE is not available. backend:AArch64 backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#168097 by paulwalker-arm was merged Nov 25, 2025 Loading…
[llvm][ARM] Allow MOVT and MOVW on the offset between two labels backend:ARM
#168072 by hwti was merged Nov 18, 2025 Loading…
[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168029 by arcbbb was merged Nov 19, 2025 Loading…
DAG: Use poison in SplitVecRes_VP_LOAD_FF backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167753 by arsenm was merged Nov 15, 2025 Loading…
DAG: Use poison when legalizing scalar_to_vector results backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167751 by arsenm was merged Nov 15, 2025 Loading…
[CodeGen] Use VirtRegOrUnit where appropriate (NFCI) backend:AMDGPU backend:ARM llvm:codegen llvm:regalloc
#167730 by s-barannikov was merged Nov 13, 2025 Loading…
[AArch64] Remove FEAT_TME assembly and ACLE support backend:AArch64 backend:ARM backend:X86 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category lldb llvm:ir
#167687 by jthackray was merged Nov 14, 2025 Loading…
DAG: Use poison when widening build_vector backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167631 by arsenm was merged Nov 12, 2025 Loading…
[ARM][BPF][Lanai][MSP430] Use MCRegister::id() to avoid an implicit cast. NFC backend:ARM backend:Lanai backend:MSP430
#167537 by topperc was merged Nov 11, 2025 Loading…
Reland "[clang] Refactor option-related code from clangDriver into new clangOptions library" (#167348) backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:X86 bazel "Peripheral" support tier build system: utils/bazel clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category clang-tools-extra clangd flang:driver flang Flang issues not falling into any other category lldb llvm:mc Machine (object) code
#167374 by naveen-seth was merged Nov 10, 2025 Loading…
Revert "[clang] Refactor option-related code from clangDriver into new clangOptions library" backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:X86 bazel "Peripheral" support tier build system: utils/bazel clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category clang-tools-extra clangd flang:driver flang Flang issues not falling into any other category lldb llvm:mc Machine (object) code
#167348 by naveen-seth was merged Nov 10, 2025 Loading…
Remove unused standard header inclusion: <iterator>, <utility>, <type_traits> backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:RISC-V backend:SPIR-V backend:SystemZ backend:X86 debuginfo llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:binary-utilities llvm:codegen llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:mc Machine (object) code llvm:regalloc llvm:support llvm:transforms PGO Profile Guided Optimizations platform:windows tablegen tools:llvm-exegesis xray
#167318 by serge-sans-paille was closed Nov 11, 2025 Loading…
[Target] Fix misleading indentation (NFC) backend:AArch64 backend:ARM backend:Hexagon backend:MIPS
#167206 by kazutakahirata was merged Nov 9, 2025 Loading…
Previous Next
ProTip! Follow long discussions with comments:>50.