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[AMDGPU] Enable copy from VCC to SHARED_BASE. backend:AMDGPU
#164138 by carlobertolli was closed Oct 20, 2025 Loading…
[AMDGPU][ASAN] Handle special GVs lowering in amdgpu-sw-lower-lds backend:AMDGPU
#161827 by skc7 was closed Nov 18, 2025 Loading…
[AMDGPU][ASAN] Remove amdgpu-no-flat-scratch-init attribute from lowered kernels in amdgpu-sw-lower-lds pass backend:AMDGPU
#160541 by skc7 was closed Oct 3, 2025 Loading…
[AMDGPU] Fix code sequence for barrier start in GFX10+ CU Mode backend:AMDGPU
#160501 by Pierre-vh was closed Oct 2, 2025 Loading…
[AMDGPU] Use table strategy for LowerModuleLDSPass at O0 backend:AMDGPU
#160181 by hjagasiaAMD was closed Oct 2, 2025 Loading…
[mlir][AMDGPU] Improve masked_load(..., broadcast(...), ...) handling backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#159635 by krzysz00 was closed Sep 19, 2025 Loading…
[ROCDL] Added rocdl.fmed3 -> Intrinsic::amdgcn_fmed3 backend:AMDGPU clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir mlir:llvm mlir
#157748 by keshavvinayak01 was closed Sep 17, 2025 • Draft
[mlir][ArithToAMDGPU] limit scaling truncf/extf support to gfx950 backend:AMDGPU mlir:gpu mlir
#155431 by Muzammiluddin-Syed-ECE was merged Sep 17, 2025 Loading…
[Driver][AMDGPU][HIP][SPIRV] Disable optimizations for AMDGCN SPIR-V backend:AMDGPU clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#154765 by AlexVlx was merged Sep 18, 2025 Loading…
[AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts backend:AMDGPU
#153143 by broxigarchen was merged Aug 14, 2025 Loading…
[AMDGPU] Add pass to align inner loops backend:AMDGPU llvm:globalisel
#152356 by hjagasiaAMD was closed Aug 11, 2025 Loading…
[AMDGPU] Support function attribute to override postRA scheduling direction backend:AMDGPU llvm:codegen
#147708 by harrisonGPU was merged Aug 1, 2025 Loading…
[AMDGPU] Illegal VGPR to SGPR copy backend:AMDGPU
#144008 by isakhilesh was closed Sep 15, 2025 Loading…
[NFC][AMDGPU] Convert amdpal.ll to autogenerated CHECK lines backend:AMDGPU
#141026 by harrisonGPU was closed May 22, 2025 Loading…
[AMDGPU] Handle unset/max flat workgroup size in waves/EU backend:AMDGPU
#139955 by npanchen was closed May 17, 2025 Loading…
[AMDGPU] Optimize LDS DMA soft waitcnt backend:AMDGPU
#138802 by kerbowa was closed Jul 31, 2025 Loading…
[AA] Make alias check more accurately. backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding
#137747 by fengfeng09 was closed May 2, 2025 Loading…
Stop abusing Twine in DiagnosticInfo backend:AMDGPU backend:DirectX llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) PGO Profile Guided Optimizations
[AMDGPU] Re-apply: Implement vop3p complex pattern optmization for gisel backend:AMDGPU llvm:globalisel
#136262 by Shoreshen was merged Jul 4, 2025 Loading…
[IR][ASMParser] Use default AS for alloca without explicit AS backend:AMDGPU clang:openmp OpenMP related changes to Clang llvm:asmparser llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms
#135786 by ritter-x2a was closed Apr 16, 2025 Loading…
[AMDGPU] Support bottom-up postRA scheduing. backend:AMDGPU
#135295 by harrisonGPU was merged Jun 5, 2025 Loading…
[AMDGPU] Enable vectorization of i8 values. backend:AMDGPU clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#134934 by doru1004 was merged Jun 26, 2025 Loading…
AMDGPU: Make v2f64 -> v2f16 conversion Legal only when unsafe fast math is set backend:AMDGPU
#134738 by changpeng was closed Aug 4, 2025 Loading…
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