- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[LV, VP]VP intrinsics support for the Loop Vectorizer + adding new tail-folding mode using EVL. backend:PowerPC backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#76172 by alexey-bataev was merged Apr 4, 2024 Loading…
[VPlan] Update scalar induction resume values in VPlan. backend:PowerPC backend:SystemZ llvm:transforms vectorizers
#110577 by fhahn was merged Dec 6, 2024 Loading…
[VPlan] Compute induction end values in VPlan. backend:PowerPC backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#112145 by fhahn was merged Dec 29, 2024 Loading…
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part I) backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:X86 llvm:transforms
#96878 by KanRobert was merged Aug 29, 2024 Loading…
[VPlan] Add initial CFG simplification, removing BranchOnCond true. backend:PowerPC backend:SystemZ llvm:transforms vectorizers
#106748 by fhahn was merged Apr 4, 2025 Loading…
[VPlan] Simplify Plan's entry in removeBranchOnConst. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#154510 by fhahn was merged Sep 18, 2025 Loading…
[LoopVectorizer] Prune VFs based on plan register pressure backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#132190 by SamTebbs33 was merged May 19, 2025 Loading…
[clang] Better bitfield access units backend:AArch64 backend:ARM backend:loongarch backend:PowerPC backend:SystemZ backend:WebAssembly clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category
#65742 by urnathan was closed Mar 29, 2024 Loading…
[IR] Initial introduction of memset_pattern backend:PowerPC llvm:ir llvm:transforms
#97583 by asb was merged Nov 15, 2024 Loading…
[VPlan] Introduce CSE pass backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#151872 by artagnon was merged Sep 2, 2025 Loading…
[DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x, c1)), c2) and folding (shl(sext(add x, c1)), c2) in some scenarios backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#101294 by LiqinWeng was merged Dec 10, 2024 Loading…
[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode backend:AArch64 backend:AMDGPU backend:PowerPC llvm:SelectionDAG SelectionDAGISel as well
#122741 by diggerlin was merged Apr 21, 2025 Loading…
Promote 32bit pseudo instr that infer extsw removal to 64bit in PPCMIPeephole backend:PowerPC
#85451 by diggerlin was merged Oct 31, 2024 Loading…
[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. backend:PowerPC llvm:transforms vectorizers
#95305 by fhahn was merged Sep 10, 2024 Loading…
[VPlan] Introduce constant folder in simplifyRecipe backend:PowerPC backend:SystemZ llvm:transforms vectorizers
#125365 by artagnon was merged May 20, 2025 Loading…
Patch series to reapply #118734 and substantially improve it backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:static analyzer clang Clang issues not falling into any other category
#120534 by chandlerc was closed Feb 4, 2025 Loading…
[CGP]: Optimize mul.overflow. backend:AArch64 backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen
#148343 by hassnaaHamdi was merged Nov 18, 2025 Loading…
[RegAlloc] Scale the spill weight by target factor backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 debuginfo llvm:regalloc
#113675 by wangpc-pp was merged Mar 13, 2025 Loading…
[Codegen][LegalizeIntegerTypes] Improve shift through stack backend:AArch64 backend:PowerPC backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#96151 by futog was merged Sep 23, 2024 Loading…
[AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. backend:PowerPC clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#80069 by diggerlin was merged Feb 22, 2024 Loading…
[VPlan] Make CanIV part of region. backend:AArch64 backend:PowerPC llvm:transforms vectorizers
#144803 by fhahn was closed Oct 2, 2025 Loading…
[RFC] implement convergence control in MIR using SelectionDAG backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:Sparc llvm:adt llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support
#71785 by ssahasra was merged Feb 21, 2024 Loading…
[VPlan] Simplify branch on False in VPlan transform (NFC). backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#140409 by fhahn was merged May 31, 2025 Loading…
Previous Next
ProTip! Mix and match filters to narrow down what you’re looking for.