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[CodeGen] Really renumber slot indexes before register allocation backend:AArch64 backend:AMDGPU backend:ARM backend:AVR backend:CSKY backend:Hexagon backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:VE backend:X86 llvm:globalisel llvm:transforms
#67038 by jayfoad was merged Oct 9, 2023 Loading… updated Oct 9, 2023
[AVR] Fix shift node descriptions backend:AVR llvm:SelectionDAG SelectionDAGISel as well
#117456 by s-barannikov was merged Nov 24, 2024 Loading… updated Nov 24, 2024
[AVR] Remove extra ROL / ROR operands backend:AVR
#117510 by s-barannikov was merged Nov 25, 2024 Loading… updated Nov 25, 2024
AVR: Move runtime libcall name setting out of TargetLowering backend:AVR llvm:ir
#142545 by arsenm was merged Jun 4, 2025 Loading… updated Jun 4, 2025
AVR: Add llvm.sincos intrinsic test backend:AVR
#148601 by arsenm was merged Jul 25, 2025 Loading… updated Jul 25, 2025
AVR: Do not add target specific STI member to AVRAsmParser backend:AVR
#156442 by arsenm was merged Sep 2, 2025 Loading… updated Sep 2, 2025
[AVR] Remove implicit conversions of MCRegister to unsigned. NFC backend:AVR
#167566 by topperc was merged Nov 11, 2025 Loading… updated Nov 11, 2025
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