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[Sparc] Change register spelling to lowercase (NFC) backend:Sparc
#65464 by s-barannikov was merged Sep 7, 2023 Loading… updated Sep 7, 2023
[Sparc] Replace some CAS instructions with InstAlias backend:Sparc llvm:mc Machine (object) code
#65588 by s-barannikov was merged Sep 9, 2023 Loading… updated Sep 9, 2023
[InlineAsm] refactor InlineAsm class NFC backend:ARM backend:Sparc backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#65649 by nickdesaulniers was merged Sep 11, 2023 Loading… updated Sep 11, 2023
reland [InlineAsm] wrap ConstraintCode in enum class NFC backend:AArch64 backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#66264 by nickdesaulniers was merged Sep 13, 2023 Loading… updated Sep 14, 2023
[Sparc] Don't emit __multi3 on 32-bit SPARC backend:Sparc
#66362 by rorth was merged Sep 15, 2023 Loading… updated Sep 15, 2023
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category debuginfo flang:driver flang:openmp flang Flang issues not falling into any other category libc++abi libc++abi C++ Runtime Library. Not libc++. lld:COFF lld:ELF lld:MachO lld:wasm lld lldb llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well LTO Link time optimization (regular/full LTO or ThinLTO) mlir:core MLIR Core Infrastructure mlir:execution-engine mlir:gpu mlir:llvm mlir platform:windows tools:llvm-exegesis
#66295 by aeubanks was merged Sep 14, 2023 Loading… updated Sep 15, 2023
[Sparc] Remove LEA instructions (NFCI) backend:Sparc
#65850 by s-barannikov was merged Sep 20, 2023 Loading… updated Sep 20, 2023
[Sparc] Remove Subtarget member of SparcTargetMachine backend:Sparc
#66876 by s-barannikov was merged Sep 25, 2023 Loading… updated Sep 25, 2023
[TargetLowering] Deduplicate choosing InlineAsm constraint between ISels backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:RISC-V backend:Sparc backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#67057 by nickdesaulniers was merged Sep 25, 2023 Loading… updated Sep 26, 2023
[Sparc] Replace CMP instructions with InstAlias (NFCI) backend:Sparc
#66859 by s-barannikov was merged Oct 9, 2023 Loading… updated Oct 9, 2023
[CodeGen] Really renumber slot indexes before register allocation backend:AArch64 backend:AMDGPU backend:ARM backend:AVR backend:CSKY backend:Hexagon backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:VE backend:X86 llvm:globalisel llvm:transforms
#67038 by jayfoad was merged Oct 9, 2023 Loading… updated Oct 9, 2023
[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) backend:Sparc
#66851 by s-barannikov was merged Oct 10, 2023 Loading… updated Oct 10, 2023
[MachineBasicBlock] Fix use after free in SplitCriticalEdge backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:WebAssembly backend:X86
#66188 by perlfu was closed Oct 11, 2023 Loading… updated Oct 11, 2023
[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#76708 by asb was merged Jan 2, 2024 Loading… updated Jan 2, 2024
[RFC][SelectionDAG] Add and use SDNode::getAsZExtVal() helper backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#76710 by asb was merged Jan 9, 2024 Loading… updated Jan 9, 2024
[SPARC] Consume Clang issues not falling into any other category
tune-cpu directive in the backend backend:Sparc clang #77195 by koachan was merged Jan 13, 2024 Loading… updated Jan 15, 2024
[SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target backend:Sparc
#78280 by koachan was merged Jan 16, 2024 Loading… updated Jan 16, 2024
[CodeGen] Add code new pm code stubs for all backends backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:SPIR-V backend:WebAssembly backend:X86
#78552 by paperchalice was closed Jan 18, 2024 Loading… updated Jan 20, 2024
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V backend:Sparc backend:X86
#80339 by preames was merged Feb 2, 2024 Loading… updated Feb 2, 2024
[SPARC] Support reserving arbitrary general purpose registers backend:Sparc clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#74927 by koachan was merged Feb 11, 2024 Loading… updated Feb 11, 2024
release/18.x: [SPARC] Support reserving arbitrary general purpose registers (#74927) backend:Sparc clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
[Sparc] limit MaxAtomicSizeInBitsSupported to 32 for 32-bit Sparc. backend:Sparc
#81655 by jyknight was merged Feb 13, 2024 Loading… updated Feb 14, 2024
[CodeGen] Port AtomicExpand to new Pass Manager backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 clang Clang issues not falling into any other category llvm:transforms
#71220 by Ris-Bali was merged Feb 25, 2024 Loading… updated Feb 25, 2024
[Sparc] Use generated MatchRegisterName (NFCI) backend:Sparc
#82165 by s-barannikov was merged Mar 2, 2024 Loading… updated Mar 2, 2024
[RFC] implement convergence control in MIR using SelectionDAG backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:Sparc llvm:adt llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support
#71785 by ssahasra was merged Feb 21, 2024 Loading… updated Mar 4, 2024
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