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Pull requests: llvm/llvm-project
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[X86][GlobalISel] Added support for llvm.set.rounding backend:AArch64 backend:RISC-V backend:X86 llvm:globalisel llvm:support
#156591 by JaydeepChauhan14 was merged Sep 25, 2025 Loading…
[DAGCombine][RISCV] fold select_cc seteq (and x, 1) 0, 0, -1 -> neg(and(x, 1)) backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#152062 by AZero13 was closed Aug 12, 2025 Loading…
[MC] Make .note.GNU-stack explicit for the trampoline case backend:AArch64 backend:RISC-V llvm:codegen llvm:mc Machine (object) code
#151754 by ssijaric-nv was merged Oct 4, 2025 Loading…
[MC] Relaxable Fragments Can be Linker Relaxable backend:RISC-V llvm:mc Machine (object) code
#150096 by lenary was closed Aug 7, 2025 Loading…
[RISCV] Align MCOperandPredicates with AsmParser backend:RISC-V llvm:mc Machine (object) code
#146184 by lenary was closed Jul 10, 2025 Loading…
Add clang driver changes to support MTI RISC-V backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#134065 by djtodoro was closed Apr 22, 2025 Loading…
[clang][CodeGen] Emit IR generation bugs: mangling, exceptions, etc. clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
llvm.tbaa.errno metadata during module creation backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ clang:codegen #125258 by antoniofrighetto was merged Oct 21, 2025 Loading…
[RISCV][VLOPT] Compute demanded VLs up front backend:RISC-V
#124530 by lukel97 was merged Jan 29, 2025 Loading…
[RISCV] Support [mh]edelegh CSRs backend:RISC-V llvm:mc Machine (object) code
#121634 by dong-miao was merged Feb 16, 2025 Loading…
[RISCV] Allow tail memcmp expansion backend:RISC-V
#121460 by wangpc-pp was merged Jan 3, 2025 Loading…
[llvm] Add NCD search on Array of basic blocks (NFC) backend:RISC-V llvm:support
#119355 by enoskova-sc was merged Jan 22, 2025 Loading…
[RISCV] Update matchSplatAsGather to use the index of extract_elt if in-bounds backend:RISC-V
#118873 by mikhailramalho was closed Jan 21, 2025 Loading…
[RISCV][TTI] Implement instruction cost for vp.reduce.* backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#114184 by ElvisWang123 was closed Nov 12, 2024 Loading…
[BPF] Support signed division at cpu v1 with constant divisor backend:AArch64 backend:RISC-V backend:WebAssembly backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#110627 by yonghong-song was closed Oct 1, 2024 Loading…
[RISCV] Add NutShell RV32/64 processors definition backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#102899 by owlxiao was closed Aug 12, 2024 Loading…
Use Module level target-abi to assign target features for codegenerated functions. backend:RISC-V llvm:ir llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#100833 by hiraditya was closed Feb 27, 2025 Loading…
Revert "[IR] Don't include Module.h in Analysis.h (NFC) (#97023)" backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category debuginfo llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) mlgo PGO Profile Guided Optimizations
#97129 by ZijunZhaoCCK was closed Jun 30, 2024 Loading…
[RISCV] Add processor definition for SpacemiT-X60 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#94564 by sunshaoce was merged Jun 18, 2024 Loading…
[RISCV] Use two ADDIs to do some stack pointer adjustments for special case backend:RISC-V
#94182 by ChunyuLiao was closed Apr 9, 2025 Loading…
[GISel][RISCV] Legalize
G_FREM to use fmod backend:RISC-V llvm:globalisel #93063 by dtcxzyw was merged May 23, 2024 Loading…
[RISCV] Check only demanded VTYPE fields in needVSETVLIPHI backend:RISC-V
#90168 by lukel97 was closed Jun 25, 2024 Loading…
[RISCV][TTI] Support fdiv/udiv/sdiv/srem/urem in getArithmeticInstrCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#89170 by arcbbb was merged May 13, 2024 Loading…
[Exegesis][RISCV] Add RISCV support for llvm-exegesis backend:RISC-V bazel "Peripheral" support tier build system: utils/bazel tools:llvm-exegesis
#89047 by AnastasiyaChernikova was merged Dec 18, 2024 Loading…
Add diagnostic help for inline asm operand constraint 'H' backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 llvm:ir
#88248 by mahesh-attarde was closed May 3, 2024 Loading…
[RISCV] Reverse (add x, (zext c)) back to (select c, (add x, 1), x) backend:RISC-V
#87236 by lukel97 was closed Apr 2, 2024 Loading…
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