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Pull requests list

Revert "[RegAlloc] Relax the split constrain on MBB prolog" backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#169990 by ronlieb was merged Nov 29, 2025 Loading…
5
Revert "[ShrinkWrap] Modify shrink wrapping to accommodate functions terminated by no-return blocks" backend:AArch64 llvm:codegen
#169852 by asb was merged Nov 27, 2025 Loading…
1
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading…
2
[llvm] Use llvm::equal (NFC) llvm:codegen
#169173 by kazutakahirata was merged Nov 22, 2025 Loading…
[CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. backend:RISC-V backend:X86 llvm:codegen
#168777 by topperc was merged Nov 20, 2025 Loading…
9
Test PR labeller github:workflow llvm:codegen llvm:regalloc
#168663 by boomanaiden154 was closed Nov 19, 2025 Loading…
2
[RegAlloc] Fix the terminal rule check for interfere with DstReg backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168661 by hstk30-hw was merged Nov 23, 2025 Loading…
35
CodeGen: Move libcall lowering configuration to subtarget backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168621 by arsenm was merged Nov 25, 2025 Loading…
6
CodeGen: Add subtarget to TargetLoweringBase constructor backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168620 by arsenm was merged Nov 19, 2025 Loading…
10
Introduce DwarfUnit::addBlock helper method debuginfo llvm:codegen
#168446 by tromey was merged Nov 18, 2025 Loading…
11
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:loongarch backend:PowerPC backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168353 by sdesmalen-arm was merged Nov 24, 2025 Loading…
26
[CodeGen] Remove a redundant declaration (NFC) llvm:codegen
#168285 by kazutakahirata was merged Nov 16, 2025 Loading…
1
[RegAlloc] Relax the split constrain on MBB prolog backend:AMDGPU backend:X86 llvm:codegen llvm:regalloc
#168259 by LuoYuanke was merged Nov 28, 2025 Loading…
20
[MLGO] Fully Remove MLRegalloc Experimental Features llvm:codegen mlgo
#168252 by boomanaiden154 was merged Nov 17, 2025 Loading…
2
[GlobalMerge] add a command to force global merge backend:ARM llvm:codegen
#168231 by Zhenhang1213 was closed Nov 20, 2025 Loading…
5
[revert][CodeGen] add a command to force global merge backend:ARM llvm:codegen
#168230 by Zhenhang1213 was merged Nov 15, 2025 Loading…
1
[RDF] Rename RegisterId field in RegisterRef Reg->Id. NFC backend:Hexagon llvm:codegen
#168154 by topperc was merged Nov 15, 2025 Loading…
3
opt: Fix bad merge of #167996 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:codegen
#168110 by arsenm was merged Nov 14, 2025 Loading…
3
[RDF] RegisterRef/RegisterId improvements. NFC llvm:codegen
#168030 by topperc was merged Nov 14, 2025 Loading…
9
RuntimeLibcalls: Move VectorLibrary handling into TargetOptions clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:ir
#167996 by arsenm was merged Nov 14, 2025 Loading…
93
[RegAllocGreedy] Use MCRegister instead of MCPhysReg. NFC llvm:codegen
#167974 by topperc was merged Nov 13, 2025 Loading…
1
[CodeGen] Turn MCRegUnit into an enum class (NFC) backend:AMDGPU backend:X86 llvm:codegen llvm:mc Machine (object) code llvm:regalloc
#167943 by s-barannikov was merged Nov 16, 2025 Loading…
4
[RegAllocFast] Add helper methods for getting/setting regunit state(NFC) llvm:codegen
#167931 by s-barannikov was merged Nov 13, 2025 Loading…
[CodeGen] Add TRI::regunits() iterating over all register units (NFC) llvm:codegen llvm:mc Machine (object) code llvm:regalloc
#167901 by s-barannikov was merged Nov 13, 2025 Loading…
10
[CodeGen] Hide SparseSet<LiveRegUnit> behind a typedef (NFC) llvm:codegen
#167898 by s-barannikov was merged Nov 13, 2025 Loading…
1
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