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[SelectionDAG] Add SelectionDAG::getTypeSize. NFC backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169764 by lukel97 was merged Dec 1, 2025 Loading… updated Dec 1, 2025
[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx backend:RISC-V
#169299 by fennecJ was merged Dec 1, 2025 Loading… updated Dec 1, 2025
[RISCV] Look through copies for True operand in vmerge fold backend:RISC-V
#170077 by lukel97 was closed Dec 1, 2025 Loading… updated Dec 1, 2025
[RISCV][llvm] Correct shamt in P extension EXTRACT_VECTOR_ELT lowering backend:RISC-V
#169823 by 4vtomat was merged Dec 1, 2025 Loading… updated Dec 1, 2025
[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#169890 by arcbbb was merged Nov 30, 2025 Loading… updated Nov 30, 2025
[SelectionDAG] Remove Floating-point math llvm:SelectionDAG SelectionDAGISel as well
NoNaNsFPMath in visitFCmp backend:AArch64 backend:AMDGPU backend:MIPS backend:PowerPC backend:RISC-V backend:X86 floating-point #163519 by paperchalice was closed Nov 28, 2025 Loading… updated Nov 30, 2025
[LoopUnroll] Skip remainder loop guard if skip unrolled loop backend:AMDGPU backend:PowerPC backend:RISC-V debuginfo llvm:transforms
#156549 by jdenny-ornl was merged Oct 7, 2025 Loading… updated Nov 30, 2025
[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:X86 bazel "Peripheral" support tier build system: utils/bazel clang:as-a-library libclang and C++ API clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:modules C++20 modules and Clang Header Modules clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category clang-tools-extra clangd flang:driver flang Flang issues not falling into any other category lldb llvm:mc Machine (object) code
#165277 by naveen-seth was merged Nov 23, 2025 Loading… updated Nov 29, 2025
[RISCV] Intrinsic Support for XCVelw backend:RISC-V llvm:ir llvm:mc Machine (object) code
#129168 by realqhc was merged Nov 29, 2025 Loading… updated Nov 29, 2025
[dwarf] make dwarf fission compatible with RISCV relaxations backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:mc Machine (object) code
#164128 by daniilavdeev was closed Nov 28, 2025 Loading… updated Nov 28, 2025
[NFC][LoopVectorize] Cache result of requiresScalarEpilogue backend:RISC-V llvm:transforms vectorizers
#108981 by david-arm was closed Nov 28, 2025 Loading… updated Nov 28, 2025
[VPlan] Skip uses-scalars restriction if one of ops needs broadcast. backend:RISC-V llvm:transforms vectorizers
#168246 by fhahn was merged Nov 28, 2025 Loading… updated Nov 28, 2025
[TTI][Vectorize] Migrate masked/gather-scatter/strided/expand-compress costing (NFCI) backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#165532 by arcbbb was merged Nov 28, 2025 Loading… updated Nov 28, 2025
[VPlan] Handle scalar VPWidenPointerInd in convertToConcreteRecipes. backend:RISC-V llvm:transforms vectorizers
#169338 by fhahn was merged Nov 27, 2025 Loading… updated Nov 28, 2025
[TTI] Use MemIntrinsicCostAttributes for getExpandCompressMemoryOpCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#168677 by arcbbb was merged Nov 28, 2025 Loading… updated Nov 28, 2025
[RegAlloc] Remove default restriction on non-trivial rematerialization backend:AArch64 backend:ARM backend:RISC-V backend:SystemZ backend:X86 llvm:codegen llvm:globalisel
#159211 by lukel97 was merged Oct 4, 2025 Loading… updated Nov 28, 2025
[LLD] Add support for statically resolved vendor-specific RISCV relocations. backend:RISC-V lld:ELF lld
#169273 by resistor was merged Nov 28, 2025 Loading… updated Nov 28, 2025
[VPlan] Optimize LastActiveLane to EVL - 1 backend:RISC-V llvm:transforms vectorizers
#169766 by lukel97 was merged Nov 27, 2025 Loading… updated Nov 27, 2025
Reland [VPlan] Handle WidenGEP in narrowToSingleScalars backend:RISC-V llvm:transforms vectorizers
#167880 by artagnon was merged Nov 24, 2025 Loading… updated Nov 27, 2025
Revert [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#169653 by daniilavdeev was merged Nov 26, 2025 Loading… updated Nov 26, 2025
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)" backend:RISC-V llvm:transforms vectorizers
#168738 by lukel97 was closed Nov 26, 2025 Loading… updated Nov 26, 2025
[MC][RISCV] Add missing Predicates for NDS_FMV_BF16_X backend:RISC-V
#169662 by sunshaoce was merged Nov 26, 2025 Loading… updated Nov 26, 2025
CodeGen: Make all targets override pseudos with pointers backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:SelectionDAG SelectionDAGISel as well tablegen
#159881 by arsenm was merged Nov 26, 2025 Loading… updated Nov 26, 2025
[VPlan] Hoist predicated loads with complementary masks. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168373 by fhahn was merged Nov 26, 2025 Loading… updated Nov 26, 2025
[VPlan] Use DL index type consistently for GEPs backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#169396 by artagnon was merged Nov 26, 2025 Loading… updated Nov 26, 2025
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