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Pull requests: llvm/llvm-project
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[GISel][Inlineasm] Support inlineasm i/s constraint for symbols backend:AArch64 llvm:globalisel
#170094 opened Dec 1, 2025 by KRM7 Loading…
[AArch64] Improve select dagcombine backend:AArch64
#169925 opened Nov 28, 2025 by huntergr-arm Loading…
[llvm-exegesis] Add AArch64 operand initializers, SetRegTo backend:AArch64 tools:llvm-exegesis
#169912 opened Nov 28, 2025 by simonwallis2 Loading…
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading…
[AArch64][ARM] Optimize more Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
tbl/tbx calls into shufflevector backend:AArch64 backend:ARM llvm:instcombine #169748 opened Nov 26, 2025 by valadaptive Loading…
Reduced neon non-const strided load cost backend:AArch64
#169731 opened Nov 26, 2025 by mwlon Loading…
[WoA] Remove extra barriers after ARM LSE instructions with MSVC backend:AArch64 llvm:codegen
#169596 opened Nov 26, 2025 by UsmanNadeem Loading…
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading…
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
[SelectionDAG] Fix unsafe cases for loop.dependence.{war/raw}.mask backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#168565 opened Nov 18, 2025 by SamTebbs33 Loading…
[InterleavedAccess] Construct interleaved access store with shuffles backend:AArch64 llvm:codegen llvm:transforms
#167737 opened Nov 12, 2025 by ram-NK Loading…
[LV][AArch64] Improve strided access vectorization for AArch64 SVE backend:AArch64 llvm:transforms SVE ARM Scalable Vector Extensions vectorizers
#164205 opened Oct 20, 2025 by kinoshita-fj • Draft
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading…
[AArch64] Add bitcasts for lowering saturating add/sub and shift intrinsics. backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#161840 opened Oct 3, 2025 by Lukacma Loading…
[AArch64] Explicitly mark ADDS, ANDS, SUBS, etc as binops backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#160170 opened Sep 22, 2025 by AZero13 Loading…
[LV] Add on extra cost for scalarising math calls in vector loops backend:AArch64 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#158611 opened Sep 15, 2025 by david-arm Loading…
[LV] Add a flag to conservatively choose a larger vector factor when maximizing bandwidth backend:AArch64 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#156012 opened Aug 29, 2025 by ytmukai Loading…
[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) backend:AArch64 backend:AMDGPU llvm:codegen llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well tablegen
#155107 opened Aug 23, 2025 by DenisGZM Loading…
[SelectionDAG] Use Magic Algorithm for Splitting UDIV/UREM by Constant backend:AArch64 backend:ARM backend:MIPS backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#154968 opened Aug 22, 2025 by mskamp Loading…
Target: Add target option for disabling
AArch64_ELFTargetObjectFile::SupportIndirectSymViaGOTPCRel backend:AArch64 #153910 opened Aug 16, 2025 by AnthonyLatsis Loading…
[AArch64] Split large loop dependence masks backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#153187 opened Aug 12, 2025 by SamTebbs33 Loading…
[LoopStrengthReduce] Encourage the creation of IVs whose increment can later be combined with memory instuctions backend:AArch64 backend:ARM llvm:transforms
#152995 opened Aug 11, 2025 by SergeyShch01 Loading…
[LoopStrengthReduce] Mitigation of issues introduced by compilation time optimization in SolveRecurse. backend:AArch64 backend:AMDGPU backend:ARM backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:transforms slow-compile
#147588 opened Jul 8, 2025 by SergeyShch01 Loading…
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading…
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