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Pull requests: llvm/llvm-project
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[SLP]Exclude non-profitable subtrees. backend:NVPTX backend:RISC-V llvm:transforms vectorizers
#162018 opened Oct 5, 2025 by alexey-bataev Loading…
[SelectionDAG][RISCV] Operations with static rounding backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#100999 opened Jul 29, 2024 by spavloff Loading…
[RISC-V] Add CSR read/write builtins backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir
#85091 opened Mar 13, 2024 by nemanjai Loading…
[SLPVectorizer] Widen strided loads. backend:RISC-V llvm:transforms vectorizers
#153074 opened Aug 11, 2025 by mgudim Loading…
[RISCV][DAG][TLI] Avoid scalarizing length decreasing shuffles backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#115532 opened Nov 8, 2024 by preames Loading…
[feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv backend:RISC-V llvm:binary-utilities llvm:mc Machine (object) code
#144620 opened Jun 18, 2025 by arjunUpatel Loading…
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading…
[RISCV] Add basic Mach-O triple support. backend:RISC-V llvm:binary-utilities llvm:mc Machine (object) code
#141682 opened May 27, 2025 by fpetrogalli Loading…
[RISCV]Do not combine to 'vw' if the number of extended instructions cannot be reduced backend:RISC-V
#159715 opened Sep 19, 2025 by ChunyuLiao Loading…
[Clang][IR] add TBAA metadata on pointer, union and array types. backend:AMDGPU backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir TBAA Type-Based Alias Analysis / Strict Aliasing
#75177 opened Dec 12, 2023 by dybv-sc Loading…
DAG: Use poison for some load/store offsets in legalizer backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#167756 opened Nov 12, 2025 by arsenm Loading…
[CodeGen] Test LICM behaviour on loop invariant loads. backend:RISC-V
#165025 opened Oct 24, 2025 by mgudim Loading…
[clang][RISCV][Zicfilp] Force user to use Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
-mcf-branch-label-scheme=unlabeled backend:RISC-V clang:frontend #152122 opened Aug 5, 2025 by mylai-mtk Loading…
[RISCV] Intrinsic Support for XCVsimd backend:RISC-V llvm:ir
#118557 opened Dec 3, 2024 by realqhc Loading…
[Asan][RISCV] Support asan check for segment load/store RVV intrinsics. backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#100931 opened Jul 28, 2024 by yetingk Loading…
[llvm-exegesis][RISCV] Deflake rvv/filter.test: split e8/e16 paths and handle empty-snippet case (ALLOW_RETRIES:1) backend:RISC-V tools:llvm-exegesis
#164924 opened Oct 24, 2025 by hank95179 Loading…
[Target] Use TableGen named argument syntax. NFC. backend:AArch64 backend:AMDGPU backend:ARM backend:m68k backend:NVPTX backend:RISC-V backend:X86
#133418 opened Mar 28, 2025 by jayfoad Loading…
[RISCV] Use proper LLA operand for constant from load backend:RISC-V
#142292 opened May 31, 2025 by cnettel Loading…
[Support] Add clang tooling generated explicit visibility macros backend:AMDGPU backend:Hexagon backend:RISC-V llvm:support
#113097 opened Oct 20, 2024 by fsfod Loading…
[bolt][riscv] Fix conditional tail call backend:RISC-V BOLT
#160042 opened Sep 22, 2025 by zengdage Loading…
[VPlan] Don't use the legacy cost model for loop conditions backend:RISC-V llvm:transforms vectorizers
#156864 opened Sep 4, 2025 by john-brawn-arm Loading…
[RISCV][TTI] Fix shift VV opcode mapping in getArithmeticInstrCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#156408 opened Sep 2, 2025 by steven-studio Loading…
[RISCV] Add a test showing that scalable offsets are not handled. backend:RISC-V
#164480 opened Oct 21, 2025 by mgudim Loading…
[RISCV] Combine concat_vectors of single element scalar_to_vector backend:RISC-V
#114366 opened Oct 31, 2024 by lukel97 Loading…
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