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Pull requests: llvm/llvm-project
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[EarlyIfCvt] Take branch probablities into consideration backend:AArch64 backend:AMDGPU backend:SystemZ backend:X86
#97808 opened Jul 5, 2024 by wangpc-pp Loading…
[TRI] Remove reserved registers in getRegPressureSetLimit backend:AMDGPU backend:ARM backend:loongarch backend:NVPTX backend:PowerPC backend:X86 llvm:globalisel llvm:regalloc llvm:transforms tablegen
#118787 opened Dec 5, 2024 by wangpc-pp Loading…
[IR] Add FPOperation intrinsic property backend:AArch64 backend:AMDGPU clang Clang issues not falling into any other category FP Bundles llvm:ir llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) tablegen
#122313 opened Jan 9, 2025 by spavloff Loading…
[PassBuilder][CodeGen] Add callback style pass buider backend:AMDGPU backend:X86
#116913 opened Nov 20, 2024 by paperchalice Loading…
[CodeGen][NPM] Stitch up loop passes in codegen pipeline backend:AMDGPU
#133050 opened Mar 26, 2025 by optimisan Loading…
[GIselValueTracking] Correctly truncate/zext G_PTRTOADDR backend:AMDGPU llvm:globalisel
#143816 opened Jun 11, 2025 by arichardson Loading…
[AMDGPU] Add BFX Formation Combines to RegBankCombiner backend:AMDGPU llvm:globalisel
#141590 opened May 27, 2025 by Pierre-vh Loading…
[AMDGPU] Add KnownBits simplification combines to RegBankCombiner backend:AMDGPU llvm:globalisel
#141591 opened May 27, 2025 by Pierre-vh Loading…
[AMDGPU] Enable IAS in the AMDGPU backend backend:AMDGPU
#85518 opened Mar 16, 2024 by brad0 Loading…
[Offload] Allow allocations to be freed without knowing their type backend:AMDGPU offload
#140889 opened May 21, 2025 by callumfare Loading…
Address Codegen bug related to marking subregister MachineOperand defines as undef backend:AMDGPU llvm:regalloc
#134929 opened Apr 8, 2025 by bababuck Loading…
[GISelValueTracking] Baseline test for G_PTRTOADDR backend:AMDGPU llvm:globalisel
#143815 opened Jun 11, 2025 by arichardson Loading…
[RISCV][GlobalISel][TargetLowering] Change SSUBO to do (LHS < RHS) XOR (RESULT < 0) backend:AMDGPU backend:RISC-V backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#150872 opened Jul 28, 2025 by AZero13 Loading…
[NVPTX] Print SyncScope::ID if out of bounds backend:AMDGPU backend:NVPTX llvm:ir
#109871 opened Sep 24, 2024 by gonzalobg Loading…
[AMDGPU] Allow intrinsics llvm.amdgcn.buffer.wbinvl1 etc for GFX940+ backend:AMDGPU
#111078 opened Oct 3, 2024 by jwanggit86 Loading…
[AMDGPU] Skip debug machine instructions in AMDGPU SIWholeQuadMode pass. backend:AMDGPU debuginfo
#134518 opened Apr 6, 2025 by kpyzhov Loading…
[AMDGPU][GFX12] Restrict scalar subword loads to PAL backend:AMDGPU
#117576 opened Nov 25, 2024 by jmmartinez Loading…
[AMDGPU] Switch to MF.estimateFunctionSizeInBytes() backend:AMDGPU
#127246 opened Feb 14, 2025 by rampitec Loading…
[AMDGPU] selecting v_sat_pk instruction, version 2 backend:AMDGPU
#123297 opened Jan 17, 2025 by Shoreshen Loading…
[Asan] Provide TTI hook to provide memory reference infromation of ta… backend:AMDGPU backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#127753 opened Feb 19, 2025 by HankChang736 Loading…
[AMDGPU] Allow lane-op lowering for some illegal types backend:AMDGPU
#114887 opened Nov 4, 2024 by rampitec Loading…
[CodeGen] Port MachineCFGPrinter to new pass manager backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding
#137570 opened Apr 28, 2025 by paperchalice Loading…
[AMDGPU] Do not add cost for register aligned shufflevectors backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#137052 opened Apr 23, 2025 by jrbyrnes Loading…
[SDag] Notify listeners when deleting a node backend:AMDGPU backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#66991 opened Sep 21, 2023 by s-barannikov • Draft
SelectionDAG: Fix isKnownNeverNaN for Min and Max backend:AMDGPU llvm:SelectionDAG SelectionDAGISel as well
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ProTip! Updated in the last three days: updated:>2025-11-28.