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[ARM] Introduce intrinsics for MVE vrnd under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169797 opened Nov 27, 2025 by davemgreen Loading… updated Nov 30, 2025
[ARM] Introduce intrinsics for MVE vcmp under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169798 opened Nov 27, 2025 by davemgreen Loading… updated Nov 30, 2025
[ARM] Introduce intrinsics for MVE minnm/maxnm under strict-fp. backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169795 opened Nov 27, 2025 by davemgreen Loading… updated Nov 30, 2025
[StackProtector] Introduce stack-protect-refinement pass to remove unnecessary protections. backend:AArch64 backend:ARM backend:X86 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category debuginfo llvm:globalisel llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#150390 opened Jul 24, 2025 by Mermen Loading… updated Nov 29, 2025
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Nov 28, 2025
[AArch64][ARM] Move ARM-specific InstCombine transforms to new module backend:AArch64 backend:ARM llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169589 opened Nov 26, 2025 by valadaptive Loading… updated Nov 28, 2025
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading… updated Nov 28, 2025
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading… updated Nov 28, 2025
[ARM] enable FENV_ACCESS pragma support for hard-float targets backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:globalisel
#137101 opened Apr 24, 2025 by Varnike Loading… updated Nov 28, 2025
[clang][DebugInfo] Add virtual call-site target information in DWARF. backend:AArch64 backend:ARM backend:MIPS backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo lldb llvm:binary-utilities llvm:codegen llvm:ir
#167666 opened Nov 12, 2025 by CarlosAlbertoEnciso Loading… updated Nov 27, 2025
[ARM] Recognize abi tag module flags backend:ARM
#161306 opened Sep 30, 2025 by paperchalice Loading… updated Nov 27, 2025
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading… updated Nov 27, 2025
[AArch64][ARM] Optimize more Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
tbl/tbx calls into shufflevector backend:AArch64 backend:ARM llvm:instcombine #169748 opened Nov 26, 2025 by valadaptive Loading… updated Nov 27, 2025
[AtomicExpand] Add bitcasts when expanding load atomic vector backend:ARM backend:X86 llvm:codegen llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#148900 opened Jul 15, 2025 by jofrn Loading… updated Nov 26, 2025
Fixes inlining issue in armv7 backend:ARM llvm:transforms
#169337 opened Nov 24, 2025 by CrooseGit Loading… updated Nov 26, 2025
RuntimeLibcalls: Add entries for stack probe functions backend:AArch64 backend:ARM backend:X86 llvm:ir
#167453 opened Nov 11, 2025 by arsenm Loading… updated Nov 25, 2025
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading… updated Nov 25, 2025
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading… updated Nov 25, 2025
[FMV][AArch64] Allow user to override version priority. backend:AArch64 backend:ARM backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms tablegen
#150267 opened Jul 23, 2025 by labrinea Loading… updated Nov 24, 2025
[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:support mlgo
#151944 opened Aug 4, 2025 by vg0204 Loading… updated Nov 24, 2025
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading… updated Nov 24, 2025
Reland "[DebugMetadata][DwarfDebug] Support function-local types in lexical block scopes (4/7)" backend:ARM backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:static analyzer clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:ir llvm:transforms
#165032 opened Oct 24, 2025 by dzhidzhoev Loading… updated Nov 21, 2025
[ARM] Enable creation of ARMISD::CMN nodes backend:ARM
#163223 opened Oct 13, 2025 by AZero13 Loading… updated Nov 18, 2025
[SelectionDAG] Optimize BSWAP yet again once more backend:ARM llvm:SelectionDAG SelectionDAGISel as well
#165292 opened Oct 27, 2025 by AZero13 Loading… updated Nov 17, 2025
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