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Pull requests list

[llvm] Support multiple save/restore points in mir backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119357 by enoskova-sc was merged Aug 12, 2025 Loading…
219
[clang] Improve nested name specifier AST representation backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 clang:analysis clang:as-a-library libclang and C++ API clang:bytecode Issues for the clang bytecode constexpr interpreter clang:codegen IR generation bugs: mangling, exceptions, etc. clang:dataflow Clang Dataflow Analysis framework - https://clang.llvm.org/docs/DataFlowAnalysisIntro.html clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:modules C++20 modules and Clang Header Modules clang:openmp OpenMP related changes to Clang clang:static analyzer clang Clang issues not falling into any other category clang-tidy clang-tools-extra clangd coroutines C++20 coroutines debuginfo HLSL HLSL Language Support libc++ libc++ C++ Standard Library. Not GNU libstdc++. Not libc++abi. lldb
#147835 by mizvekov was merged Aug 9, 2025 Loading…
4
@mizvekov
160
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part I) backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:X86 llvm:transforms
#96878 by KanRobert was merged Aug 29, 2024 Loading…
138
[Clang][AArch64] Add customisable immediate range checking to NEON backend:AArch64 backend:ARM clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#100278 by SpencerAbson was merged Sep 6, 2024 Loading…
120
[ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing backend:ARM llvm:mc Machine (object) code
#83436 by AlfieRichardsArm was merged Mar 18, 2024 Loading…
118
[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:NVPTX backend:PowerPC backend:SPIR-V backend:WebAssembly backend:X86 debuginfo llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms llvm Umbrella label for LLVM issues
#86149 by SLTozer was merged Aug 29, 2024 Loading…
@SLTozer
109
[LLVM][Clang][AArch64] Implement AArch64 build attributes backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V clang Clang issues not falling into any other category llvm:binary-utilities llvm:mc Machine (object) code llvm:support
#118771 by sivan-shani was merged Jan 22, 2025 Loading…
94
[clang] Better bitfield access units backend:AArch64 backend:ARM backend:loongarch backend:PowerPC backend:SystemZ backend:WebAssembly clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category
#65742 by urnathan was closed Mar 29, 2024 Loading…
90
[IA][RISCV] Add support for vp.load/vp.store with shufflevector backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:ir
#135445 by mshockwave was merged May 7, 2025 Loading…
89
[llvm][ARM]Add widen global arrays pass backend:ARM llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#107120 by nasherm was merged Oct 17, 2024 Loading…
85
[DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x, c1)), c2) and folding (shl(sext(add x, c1)), c2) in some scenarios backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#101294 by LiqinWeng was merged Dec 10, 2024 Loading…
84
[KnownBits] Make nuw and nsw support in computeForAddSub optimal backend:AArch64 backend:AMDGPU backend:ARM llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms
#83382 by goldsteinn was closed Mar 5, 2024 Loading…
77
Patch series to reapply #118734 and substantially improve it backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:loongarch backend:m68k backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:static analyzer clang Clang issues not falling into any other category
#120534 by chandlerc was closed Feb 4, 2025 Loading…
73
[CGP]: Optimize mul.overflow. backend:AArch64 backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen
#148343 by hassnaaHamdi was merged Nov 18, 2025 Loading…
73
[RegAlloc] Scale the spill weight by target factor backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 debuginfo llvm:regalloc
#113675 by wangpc-pp was merged Mar 13, 2025 Loading…
1
70
[DAG] Combine store + vselect to masked_store backend:AArch64 backend:ARM backend:RISC-V backend:X86 llvm:codegen llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#145176 by abhishek-kaushik22 was merged Aug 4, 2025 Loading…
68
[NVPTX] Lower LLVM masked vector loads and stores to PTX backend:AArch64 backend:ARM backend:Hexagon backend:NVPTX backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#159387 by dakersnar was merged Nov 25, 2025 Loading…
67
[IR] Add llvm.sincos intrinsic backend:AArch64 backend:ARM llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support
#109825 by MacDue was merged Oct 29, 2024 Loading…
59
Bfi precision backend:AArch64 backend:AMDGPU backend:ARM backend:X86 compiler-rt llvm:analysis Includes value tracking, cost tables and constant folding llvm:support llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO) PGO Profile Guided Optimizations
#66285 by MatzeB was merged Oct 25, 2023 Loading…
58
[RFC] implement convergence control in MIR using SelectionDAG backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:RISC-V backend:Sparc llvm:adt llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support
#71785 by ssahasra was merged Feb 21, 2024 Loading…
58
[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF backend:AArch64 backend:AMDGPU backend:ARM backend:SystemZ backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#83039 by Nirhar was merged Jul 8, 2024 Loading…
1
58
[llvm] Extract and propagate callee_type metadata backend:AArch64 backend:ARM backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#87575 by Prabhuk was merged Jul 30, 2025 Loading…
56
[MC,ELF] Emit warning if a string constant contains newline char backend:AMDGPU backend:ARM backend:WebAssembly llvm:mc Machine (object) code
#98060 by chestnykh was merged Jul 16, 2024 Loading…
55
[CGData] Outlined Hash Tree backend:AArch64 backend:ARM llvm:support
#89792 by kyulee-com was merged Jul 7, 2024 Loading…
54
[LV] Bundle sub reductions into VPExpressionRecipe backend:AArch64 backend:ARM llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms llvm:vectorcombine vectorizers
#147255 by SamTebbs33 was merged Sep 1, 2025 Loading…
54
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