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[RISCV] Apply
IsSignExtendingOpW = 1 on fcvtmod.w.d backend:RISC-V #69633 by mshockwave was merged Oct 19, 2023 Loading…
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir llvm:mc Machine (object) code llvm:support
#68295 by 4vtomat was merged Oct 20, 2023 Loading…
[RISCV] Replace PostRAScheduler with PostMachineScheduler backend:RISC-V
#68696 by wangpc-pp was merged Oct 19, 2023 Loading…
[RISCV] Fix assertion failure from performBUILD_VECTORCombine when the binop is a shift. backend:RISC-V
#69349 by topperc was merged Oct 19, 2023 Loading…
[RISCV] Remove FrameIndex case in lui+addi MacroFusion backend:RISC-V
#68701 by wangpc-pp was merged Oct 19, 2023 Loading…
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category debuginfo flang:driver flang:openmp flang Flang issues not falling into any other category libc++abi libc++abi C++ Runtime Library. Not libc++. lld:COFF lld:ELF lld:MachO lld:wasm lld lldb llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well LTO Link time optimization (regular/full LTO or ThinLTO) mlir:core MLIR Core Infrastructure mlir:execution-engine mlir:gpu mlir:llvm mlir platform:windows tools:llvm-exegesis
#66295 by aeubanks was merged Sep 14, 2023 Loading…
[AMDGPU] [SIFrameLowering] Use LiveRegUnits instead of LivePhysRegs backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V llvm:regalloc
#65962 by prtaneja was merged Sep 21, 2023 Loading…
[SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore. backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#66567 by topperc was closed Sep 18, 2023 Loading…
[SelectionDAG][RISCV][PowerPC][X86] Use TargetConstant for immediates for ISD::PREFETCH. backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#66601 by topperc was merged Sep 18, 2023 Loading…
[RISCV] Match gather(splat(ptr)) as zero strided load backend:RISC-V
#65769 by preames was merged Sep 8, 2023 Loading…
[MC][RISCV] Add assembly syntax highlighting for RISCV backend:RISC-V llvm:mc Machine (object) code
#65853 by dtcxzyw was merged Sep 12, 2023 Loading…
[RISCV] Optimize gather/scatter to unit-stride memop + shuffle backend:RISC-V
#66279 by preames was closed Sep 18, 2023 Loading…
[RISCV] Prefer vrgatherei16 for shuffles backend:RISC-V
#66291 by preames was closed Sep 18, 2023 Loading…
[RISCV] Improve contant materialization to end with 'not' if the cons… backend:RISC-V
#66950 by topperc was merged Sep 20, 2023 Loading…
[RISCV][GISel] Implement instruction selection for G_PHI and G_BRCOND. backend:RISC-V llvm:globalisel
#66970 by topperc was closed Sep 22, 2023 Loading…
CostModel/RISCV: tweak test for ctpop, with/without ZVBB backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding test-suite
#67013 by artagnon was merged Sep 27, 2023 Loading…
[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad backend:RISC-V
#67014 by wangpc-pp was merged Sep 22, 2023 Loading…
[RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 backend:RISC-V
#67017 by lukel97 was merged Oct 4, 2023 Loading…
CostModel/RISCV: tweak cost of vector ctpop under ZVBB backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#67020 by artagnon was merged Sep 27, 2023 Loading…
ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#67035 by artagnon was merged Sep 21, 2023 Loading…
[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask backend:RISC-V
#67037 by lukel97 was merged Sep 22, 2023 Loading…
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… backend:RISC-V llvm:globalisel
#67053 by topperc was merged Sep 22, 2023 Loading…
[TargetLowering] Deduplicate choosing InlineAsm constraint between ISels backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:RISC-V backend:Sparc backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#67057 by nickdesaulniers was merged Sep 25, 2023 Loading…
[RISCV] Truncate constants to eltwidth before checking simm5 when con… backend:RISC-V
#67062 by topperc was merged Sep 22, 2023 Loading…
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