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Pull requests list

[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading…
1
[llvm-exegesis] Make rvv/filter.test deterministic backend:RISC-V tools:llvm-exegesis
#170014 opened Nov 29, 2025 by boomanaiden154 Loading…
1
[RISCV] Update SpacemiT-X60 vector load/stores backend:RISC-V
#169936 opened Nov 28, 2025 by mikhailramalho Loading…
1
GlobalISel: Stop using TPC to check if GlobalISelAbort is enabled backend:RISC-V llvm:globalisel
#169917 opened Nov 28, 2025 by petar-avramovic Loading…
3
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading…
4
[RISCV][GISel] Fix legalize G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169877 opened Nov 28, 2025 by jacquesguan Loading…
1
[RISCV][GISel] Support select G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169789 opened Nov 27, 2025 by jacquesguan Loading…
1
[SelectionDAG] Add SelectionDAG::getTypeSize. NFC backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169764 opened Nov 27, 2025 by lukel97 Loading…
9
[RISCV] LMUL lists for indexed and strided loads backend:RISC-V
#169756 opened Nov 27, 2025 by ppenzin Loading…
7
[Exegesis][RISCV] Support C_LDSP for llvm-exegesis backend:RISC-V tools:llvm-exegesis
#169660 opened Nov 26, 2025 by sunshaoce Loading…
8
[RISCV] Rename SFB Base Feature backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#169607 opened Nov 26, 2025 by lenary Loading…
2
[RISCV] Use Zilsd Pseudos in ISel backend:RISC-V
#169580 opened Nov 25, 2025 by lenary Loading…
8
[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. backend:RISC-V
#169529 opened Nov 25, 2025 by topperc Loading…
11
optimize is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#169402 opened Nov 24, 2025 by folkertdev Loading…
1
13
[RISCV] Use vsetivli instead of x0,x0 form to retain SEW/LMUL when AVL is imm backend:RISC-V
#169307 opened Nov 24, 2025 by wangpc-pp Loading…
17
[RISCV]: Implemented softening of FCANONICALIZE backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169234 opened Nov 23, 2025 by kper Loading…
1
17
[llvm][RISCV] Make X0 register pair legal in pre-ra pass backend:RISC-V
#169164 opened Nov 22, 2025 by 4vtomat Loading…
3
[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading…
7
[RISCV] Expand X * (2^N - 2^M) where N < M backend:RISC-V
#168843 opened Nov 20, 2025 by pfusik Loading…
3
[DAG] Fold mul 0 -> 0 when expanding mul into parts. backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#168780 opened Nov 19, 2025 by davemgreen Loading…
11
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading…
78
[RISCV] Mark sincos libcalls as available for RISC-V backend:RISC-V llvm:ir
#168708 opened Nov 19, 2025 by asb Loading…
5
[CodeGen] Check physical def kill flag in MachineInstr::isDead backend:RISC-V llvm:codegen
#168684 opened Nov 19, 2025 by lukel97 Loading…
4
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading…
12
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
21
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