- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
Replace llvm.memcpy et al's i1 isVolatile with i8 VolFlags backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MSP430 backend:RISC-V backend:Sparc backend:WebAssembly backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo flang:driver flang:fir-hlfir flang:openmp flang Flang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms mlir:llvm mlir:spirv mlir PGO Profile Guided Optimizations
#65748 opened Sep 8, 2023 by urnathan Loading…
[RISCV] Select atomic_{load/store} to pseudos and expand them later backend:RISC-V
#67108 opened Sep 22, 2023 by wangpc-pp Loading…
[RISCV] Improve cleanup phase of RISCV Insert VSETVLI pass backend:RISC-V vectorizers
#67144 opened Sep 22, 2023 by simeonkr Loading…
[RISC-V][MC] Accept an absolute variable value as a CSR number backend:RISC-V llvm:mc Machine (object) code
#67377 opened Sep 25, 2023 by arichardson Loading…
[RISCV][MC] Implement ISA mapping symbols backend:RISC-V llvm:mc Machine (object) code
#67541 opened Sep 27, 2023 by joe-img Loading…
[RISCV][Zba] Optimize mul with SH*ADD backend:RISC-V
#68144 opened Oct 3, 2023 by vacmannnn Loading…
[clang] Add information about lld presence in RISCVToolchain. backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#68904 opened Oct 12, 2023 by dybv-sc Loading…
[clang] Enable --gcc-install-dir for RISCV baremetal toolchains backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#71803 opened Nov 9, 2023 by mihailo-stojanovic Loading…
[RFC] Introducing IR generation bugs: mangling, exceptions, etc. clang:dataflow Clang Dataflow Analysis framework - https://clang.llvm.org/docs/DataFlowAnalysisIntro.html clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:static analyzer clang Clang issues not falling into any other category llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
__builtin_consistent to generate AArch64 BC.cond … backend:AArch64 backend:ARM backend:loongarch backend:m68k backend:MSP430 backend:RISC-V backend:Sparc backend:SPIR-V backend:WebAssembly backend:X86 clang:analysis clang:codegen #72175 opened Nov 14, 2023 by ilinpv Loading…
[RISCV] Add macro fusions for Xiangshan backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V backend:X86 llvm:mc Machine (object) code
#72362 opened Nov 15, 2023 by wangpc-pp Loading…
[RISCV] Fix missing scaling by LMUL in cost model backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#73342 opened Nov 24, 2023 by simeonkr Loading…
[RISCV] Rematerialize load backend:RISC-V llvm:regalloc
#73924 opened Nov 30, 2023 by niwinanto Loading…
[VP][RISCV] Introduce experimental.vp.popcount and RISC-V support. backend:RISC-V llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#74294 opened Dec 4, 2023 by yetingk Loading…
[Clang][IR] add TBAA metadata on pointer, union and array types. backend:AMDGPU backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir TBAA Type-Based Alias Analysis / Strict Aliasing
#75177 opened Dec 12, 2023 by dybv-sc Loading…
[RISCV] Improve llvm.reduce.fmaximum/minimum lowering backend:RISC-V
#75484 opened Dec 14, 2023 by simeonkr Loading…
[RISCV] Fold extract_vector_elt of a load into the scalar load backend:RISC-V
#76151 opened Dec 21, 2023 by ChunyuLiao Loading…
[RISCV] Collect function features in AsmPrinter before emission (#76231) backend:RISC-V
#76437 opened Dec 27, 2023 by andcarminati Loading…
[riscv] Fix for __riscv_v_fixed_vlen in vector mask types backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#76510 opened Dec 28, 2023 by ita-sc Loading…
[RISCV] Add experimental support of Zaamo and Zalrsc backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:mc Machine (object) code llvm:support
#77424 opened Jan 9, 2024 by wangpc-pp Loading…
[MacroFusion][RISCV] Allocate same register for second instruction of fusible pair backend:RISC-V
#77461 opened Jan 9, 2024 by wangpc-pp Loading…
[CodeGen][RISCV] Make default describeLoadedValue implementation call getConstValDefinedInReg backend:RISC-V
#77611 opened Jan 10, 2024 by asb Loading…
[RISCV] Optimise spills/fills of FPR<->GPR moves backend:RISC-V
#78408 opened Jan 17, 2024 by asb Loading…
[RISCV][Clang] Added builtin support for experimental Zimop extension backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#79971 opened Jan 30, 2024 by JivanH Loading…
[Clang][RISCV] Add assumptions to vsetvli/vsetvlimax backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#79975 opened Jan 30, 2024 by wangpc-pp Loading…
Previous Next
ProTip! Add no:assignee to see everything that’s not assigned.