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Pull requests list

[Exegesis][RISCV] Add RISCV support for llvm-exegesis backend:RISC-V bazel "Peripheral" support tier build system: utils/bazel tools:llvm-exegesis
#89047 by AnastasiyaChernikova was merged Dec 18, 2024 Loading…
261
[LV, VP]VP intrinsics support for the Loop Vectorizer + adding new tail-folding mode using EVL. backend:PowerPC backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#76172 by alexey-bataev was merged Apr 4, 2024 Loading…
243
[llvm] Support multiple save/restore points in mir backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119357 by enoskova-sc was merged Aug 12, 2025 Loading…
219
[VPlan] Compute induction end values in VPlan. backend:PowerPC backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#112145 by fhahn was merged Dec 29, 2024 Loading…
184
[GISel][RISCV]Implement indirect parameter passing backend:RISC-V llvm:globalisel
#95429 by spaits was merged Jun 19, 2024 Loading…
183
[clang] Improve nested name specifier AST representation backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 clang:analysis clang:as-a-library libclang and C++ API clang:bytecode Issues for the clang bytecode constexpr interpreter clang:codegen IR generation bugs: mangling, exceptions, etc. clang:dataflow Clang Dataflow Analysis framework - https://clang.llvm.org/docs/DataFlowAnalysisIntro.html clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:modules C++20 modules and Clang Header Modules clang:openmp OpenMP related changes to Clang clang:static analyzer clang Clang issues not falling into any other category clang-tidy clang-tools-extra clangd coroutines C++20 coroutines debuginfo HLSL HLSL Language Support libc++ libc++ C++ Standard Library. Not GNU libstdc++. Not libc++abi. lldb
#147835 by mizvekov was merged Aug 9, 2025 Loading…
4
@mizvekov
160
[TableGen][DecoderEmitter] Add option to emit type-specialized code backend:AMDGPU backend:ARC backend:CSKY backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:SystemZ backend:Xtensa tablegen
#146593 by jurahul was closed Aug 30, 2025 • Draft
153
[RISCV][GlobalISel] Legalize scalable vectorized G_ADD, G_SUB, G_AND, G_OR, and G_XOR backend:RISC-V llvm:globalisel
#71400 by jiahanxie353 was closed Jan 10, 2024 Loading…
149
[llvm][RISCV] Implement Zilsd load/store pair optimization backend:RISC-V
#158640 by 4vtomat was merged Nov 21, 2025 Loading…
149
[VPlan] Model branch cond to enter scalar epilogue in VPlan. backend:RISC-V llvm:transforms vectorizers
#92651 by fhahn was merged Jul 5, 2024 Loading…
147
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#153643 by fhahn was merged Aug 26, 2025 Loading…
139
[VPlan] Replace VPRegionBlock with explicit CFG before execute (NFCI). backend:RISC-V llvm:transforms vectorizers
#117506 by fhahn was merged May 24, 2025 Loading…
132
[VPlan] Connect (MemRuntime|SCEV)Check blocks as VPlan transform (NFC). backend:RISC-V llvm:transforms vectorizers
#143879 by fhahn was merged Jul 9, 2025 Loading…
130
Move a lot of symbol code to use the symbol string pool backend:RISC-V BOLT
#115796 by jaredwy was merged Dec 5, 2024 Loading…
@lhames
128
[VPlan] Introduce recipes for VP loads and stores. backend:RISC-V llvm:transforms vectorizers
#87816 by fhahn was merged Apr 19, 2024 Loading…
128
[RISCV] Support postRA vsetvl insertion pass backend:RISC-V debuginfo
#70549 by BeMg was merged May 21, 2024 Loading…
127
[LV][VPlan] Add initial support for CSA vectorization backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#106560 by michaelmaitland was closed Dec 27, 2024 Loading…
124
[VPlan] Introduce ResumePhi VPInstruction, use to create phi for FOR. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#94760 by fhahn was merged Jul 11, 2024 Loading…
118
[VPlan] Build initial VPlan 0 using HCFGBuilder for inner loops. (NFC) backend:RISC-V llvm:transforms vectorizers
#124432 by fhahn was merged Feb 18, 2025 Loading…
117
[VPlan] Update final IV exit value via VPlan. backend:RISC-V llvm:transforms vectorizers
#112147 by fhahn was merged Jan 18, 2025 Loading…
111
[VPlan] Simplify Plan's entry in removeBranchOnConst. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#154510 by fhahn was merged Sep 18, 2025 Loading…
109
[LoopVectorizer] Prune VFs based on plan register pressure backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#132190 by SamTebbs33 was merged May 19, 2025 Loading…
107
[LLVM][MC][DecoderEmitter] Add support to specialize decoder per bitwidth backend:AMDGPU backend:RISC-V llvm:mc Machine (object) code tablegen
#154865 by jurahul was merged Sep 1, 2025 Loading…
107
[VPlan] Introduce scalar loop header in plan, remove VPLiveOut. backend:RISC-V llvm:transforms vectorizers
#109975 by fhahn was merged Oct 31, 2024 Loading…
106
[LLVM][Clang][AArch64] Implement AArch64 build attributes backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V clang Clang issues not falling into any other category llvm:binary-utilities llvm:mc Machine (object) code llvm:support
#118771 by sivan-shani was merged Jan 22, 2025 Loading…
94
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