- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading…
Group the InstrumentationTests target with other LLVM unit test targe… llvm:transforms
#170041 opened Nov 30, 2025 by LegalizeAdulthood Loading…
[NFC] Fix multi-line RUN statement in a test. llvm:transforms
#170011 opened Nov 29, 2025 by mingmingl-llvm Loading…
[WPD] Change Devirt Cutoff to use DebugCounter llvm:transforms
#170009 opened Nov 29, 2025 by boomanaiden154 Loading…
[profcheck] Fix missing profile metadata in ExpandMemCmp llvm:codegen llvm:transforms
#169979 opened Nov 29, 2025 by jinhuang1102 Loading…
[InstCombine] Try to infer type for Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
load/store when replacing memcpy llvm:instcombine #169966 opened Nov 29, 2025 by inbelic Loading…
[InstCombine] Fold Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
icmp samesign u{gt/lt} (X +nsw C2), C -> icmp s{gt/lt} X, (C - C2) llvm:instcombine #169960 opened Nov 28, 2025 by wermos Loading…
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading…
10 tasks
[LoadStoreVectorizer] Allow redundant stores backend:AMDGPU llvm:globalisel llvm:transforms vectorizers
#169946 opened Nov 28, 2025 by cmc-rep Loading…
InstCombine: fold umax/umin(shl(umax/umin(x,C1),s),C3) -> umax/umin(shl(x,s),C3) when safe (#139786) llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169943 opened Nov 28, 2025 by cs25mtech12013-commits Loading…
[InstCombine] Always fold assumes to use operand bundles llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169923 opened Nov 28, 2025 by philnik777 Loading…
[Delinearization] Add validation for large size arrays llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#169902 opened Nov 28, 2025 by kasuga-fj Loading…
[LV] Decide early between partial reduce and a regular reduction based on cost-model llvm:transforms vectorizers
#169898 opened Nov 28, 2025 by sushgokh Loading…
[TSan] Add dominance-based redundant instrumentation elimination compiler-rt:sanitizer compiler-rt:tsan Thread sanitizer compiler-rt llvm:transforms
#169897 opened Nov 28, 2025 by apaznikov Loading…
[TSan] Add escape analysis for redundant instrumentation elimination compiler-rt:sanitizer compiler-rt:tsan Thread sanitizer compiler-rt llvm:transforms
#169896 opened Nov 28, 2025 by apaznikov Loading…
Added fix to enable constant folding that is missing for math library functions (scalbln , scalbn, ldexp) llvm:transforms
#169893 opened Nov 28, 2025 by Sriharika1506 Loading…
[CoroEarly] Infer presplitcoroutine attribute for Switch-Resumed ABI clang:codegen IR generation bugs: mangling, exceptions, etc. coroutines C++20 coroutines llvm:transforms
[SLP]Enable float point math ops as copyables elements. llvm:transforms vectorizers
#169857 opened Nov 27, 2025 by alexey-bataev Loading…
[VPlan] Use wide IV if scalar lanes > 0 are used with scalable vectors. llvm:transforms vectorizers
#169796 opened Nov 27, 2025 by fhahn Loading…
[AArch64][ARM] Optimize more Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
tbl/tbx calls into shufflevector backend:AArch64 backend:ARM llvm:instcombine #169748 opened Nov 26, 2025 by valadaptive Loading…
[IndVarSimplify] Introduce
simulateFPIVTripCount to canonicalize fp loops llvm:transforms #169707 opened Nov 26, 2025 by antoniofrighetto Loading…
[MapVector] Introduce {keys,values} iterator, use in VPlan llvm:adt llvm:transforms vectorizers
#169675 opened Nov 26, 2025 by artagnon Loading…
Reland "Redesign Straight-Line Strength Reduction (SLSR) (#162930)" backend:AMDGPU backend:NVPTX llvm:transforms
#169614 opened Nov 26, 2025 by fiigii Loading…
[AArch64][ARM] Move ARM-specific InstCombine transforms to new module backend:AArch64 backend:ARM llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169589 opened Nov 26, 2025 by valadaptive Loading…
Previous Next
ProTip! Filter pull requests by the default branch with base:main.