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Pull requests: llvm/llvm-project
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[LoopVectorizer] Add support for partial reductions backend:AArch64 llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms vectorizers
#92418 by NickGuy-Arm was merged Dec 19, 2024 Loading…
[VPlan] Implement interleaving as VPlan-to-VPlan transform. llvm:transforms vectorizers
#95842 by fhahn was merged Sep 21, 2024 Loading…
[VPlan] Implement VPlan-based cost model for VPReduction, VPExtendedReduction and VPMulAccumulateReduction. llvm:transforms vectorizers
#113903 by ElvisWang123 was merged May 29, 2025 Loading…
[LV, VP]VP intrinsics support for the Loop Vectorizer + adding new tail-folding mode using EVL. backend:PowerPC backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#76172 by alexey-bataev was merged Apr 4, 2024 Loading…
Add the 'initializes' attribute langref and support llvm:adt llvm:ir llvm:transforms
#84803 by haopliu was merged Jun 21, 2024 Loading…
[LV] Vectorize selecting last IV of min/max element. llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#141431 by fhahn was merged Nov 28, 2025 Loading…
[LLVM][Instrumentation] Add numerical sanitizer clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category compiler-rt:sanitizer compiler-rt llvm:ir llvm:transforms
#85916 by alexander-shaposhnikov was merged Jun 28, 2024 Loading…
[InstrFDO][TypeProf] Implement binary instrumentation and profile read/write compiler-rt llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms PGO Profile Guided Optimizations
#66825 by mingmingl-llvm was merged Apr 1, 2024 Loading…
[InstCombine] Transform high latency, dependent FSQRT/FDIV into FMUL floating-point Floating-point math llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#87474 by sushgokh was merged Jan 17, 2025 Loading…
[VPlan] Update scalar induction resume values in VPlan. backend:PowerPC backend:SystemZ llvm:transforms vectorizers
#110577 by fhahn was merged Dec 6, 2024 Loading…
[VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) llvm:transforms vectorizers
#114292 by fhahn was merged Dec 12, 2024 Loading…
[VPlan] Dispatch to multiple exit blocks via middle blocks. llvm:transforms vectorizers
#112138 by fhahn was merged Dec 11, 2024 Loading…
[VPlan] Compute induction end values in VPlan. backend:PowerPC backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#112145 by fhahn was merged Dec 29, 2024 Loading…
[VPlan] Introduce ComputeReductionResult VPInstruction opcode. llvm:transforms vectorizers
#70253 by fhahn was merged Jan 4, 2024 Loading…
[LV] Vectorize maxnum/minnum w/o fast-math flags. backend:AArch64 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
[VPlan] Add VPExpressionRecipe, replacing extended reduction recipes. llvm:transforms vectorizers
#144281 by fhahn was merged Jul 1, 2025 Loading…
[VPlan] Model branch cond to enter scalar epilogue in VPlan. backend:RISC-V llvm:transforms vectorizers
#92651 by fhahn was merged Jul 5, 2024 Loading…
[VPlan] Move predication to VPlanTransform (NFC). llvm:transforms vectorizers
#128420 by fhahn was merged May 21, 2025 Loading…
[LV] Add initial support for vectorizing literal struct return values backend:AMDGPU llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms vectorizers
#109833 by MacDue was merged Feb 17, 2025 Loading…
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#153643 by fhahn was merged Aug 26, 2025 Loading…
[X86,SimplifyCFG] Support hoisting load/store with conditional faulting (Part I) backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:X86 llvm:transforms
#96878 by KanRobert was merged Aug 29, 2024 Loading…
[DSE] Apply initializes attribute to DSE llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#107282 by haopliu was merged Oct 24, 2024 Loading…
[InstCombine] Simplify select if it combinated and/or/xor llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#73362 by ParkHanbum was merged Apr 3, 2024 Loading…
[DTLTO][LLVM] Integrated Distributed ThinLTO (DTLTO) llvm:support llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#127749 by bd1976bris was merged May 23, 2025 Loading…
[VPlan] Replace VPRegionBlock with explicit CFG before execute (NFCI). backend:RISC-V llvm:transforms vectorizers
#117506 by fhahn was merged May 24, 2025 Loading…
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