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[SelectionDAG] Add SelectionDAG::getTypeSize. NFC backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169764 opened Nov 27, 2025 by lukel97 Loading… updated Dec 1, 2025
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#170076 opened Dec 1, 2025 by rez5427 Loading… updated Dec 1, 2025
[LLVM][CodeGen][SVE] Add lowering for ISD::[ANY,SIGN,ZERO]_EXTEND_VECTOR_INREG. backend:AArch64
#169847 opened Nov 27, 2025 by paulwalker-arm Loading… updated Dec 1, 2025
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading… updated Dec 1, 2025
[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity backend:AArch64
#169930 opened Nov 28, 2025 by AlexeyMerzlyakov Loading… updated Dec 1, 2025
[aarch64] Mix the frame pointer with the stack cookie when protecting the stack backend:AArch64 backend:X86 llvm:codegen llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#161114 opened Sep 29, 2025 by PanTao2 Loading… updated Dec 1, 2025
[AArch64][GlobalISel] Don't crash when legalising G_*MIN/G_*MAX of pointer vector backend:AArch64 llvm:globalisel
#168872 opened Nov 20, 2025 by cofibrant Loading… updated Nov 30, 2025
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading… updated Nov 30, 2025
10 tasks
[RegAlloc][AArch64] Add test case for terminal rule. NFC backend:AArch64
#170035 opened Nov 30, 2025 by hstk30-hw Loading… updated Nov 30, 2025
[AArch64] Optimize more floating-point round+convert combinations into fcvt instructions backend:AArch64
#170018 opened Nov 30, 2025 by valadaptive Loading… updated Nov 30, 2025
[AArch64] support
.arch_extension dit backend:AArch64 #169999 opened Nov 29, 2025 by folkertdev Loading… updated Nov 29, 2025
[AArch64] Fix handling of x29/x30 in inline assembly clobbers backend:AArch64
#167783 opened Nov 12, 2025 by lalinsky Loading… updated Nov 29, 2025
[StackProtector] Introduce stack-protect-refinement pass to remove unnecessary protections. backend:AArch64 backend:ARM backend:X86 clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category debuginfo llvm:globalisel llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#150390 opened Jul 24, 2025 by Mermen Loading… updated Nov 29, 2025
[llvm-exegesis] Add AArch64 operand initializers, SetRegTo backend:AArch64 tools:llvm-exegesis
#169912 opened Nov 28, 2025 by simonwallis2 Loading… updated Nov 29, 2025
[DAGCombiner] Handle type-promoted constants in SDIV exact lowering backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#169950 opened Nov 28, 2025 by SavchenkoValeriy Loading… updated Nov 28, 2025
[DAGCombiner] Handle type-promoted constants in UDIV exact lowering backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#169949 opened Nov 28, 2025 by SavchenkoValeriy Loading… updated Nov 28, 2025
[WoA] Remove extra barriers after ARM LSE instructions with MSVC backend:AArch64 llvm:codegen
#169596 opened Nov 26, 2025 by UsmanNadeem Loading… updated Nov 28, 2025
[AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes backend:AArch64 llvm:globalisel
#165546 opened Oct 29, 2025 by Lukacma Loading… updated Nov 28, 2025
[AArch64] Improve select dagcombine backend:AArch64
#169925 opened Nov 28, 2025 by huntergr-arm Loading… updated Nov 28, 2025
[AArch64][ARM] Move ARM-specific InstCombine transforms to new module backend:AArch64 backend:ARM llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#169589 opened Nov 26, 2025 by valadaptive Loading… updated Nov 28, 2025
[Clang][LLVM][AArch64]Add support for svrint{32|64}{z|x} intrinsics backend:AArch64 clang:frontend Language frontend issues, e.g. anything involving "Sema" llvm:ir
#169661 opened Nov 26, 2025 by CarolineConcatto Loading… updated Nov 28, 2025
[InterleavedAccess] Construct interleaved access store with shuffles backend:AArch64 llvm:codegen llvm:transforms
#167737 opened Nov 12, 2025 by ram-NK Loading… updated Nov 28, 2025
[AArch64] Allow single-element vector FP converts with +fprcvt backend:AArch64
#169692 opened Nov 26, 2025 by Amichaxx Loading… updated Nov 28, 2025
[LLVM][CodeGen] Remove failure cases when widening EXTRACT/INSERT_SUBVECTOR. backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well
#162308 opened Oct 7, 2025 by paulwalker-arm Loading… updated Nov 28, 2025
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