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Pull requests: llvm/llvm-project
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[SLP] Support for copyables in the reduced values backend:RISC-V llvm:transforms vectorizers
#153589 opened Aug 14, 2025 by alexey-bataev Loading… updated Nov 28, 2025
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 opened Nov 19, 2025 by arcbbb Loading… updated Nov 28, 2025
[RISCV] Add Svrsw60t59b extension backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:mc Machine (object) code
#132321 opened Mar 21, 2025 by trdthg Loading… updated Nov 28, 2025
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading… updated Nov 25, 2025
[RISCV] Enable TLSDESC by default backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
[RISCV] Support Zvfofp4min assembler version 0.1 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category
#164820 opened Oct 23, 2025 by 4vtomat Loading… updated Oct 29, 2025
[llvm-exegesis][RISCV] Deflake rvv/filter.test: split e8/e16 paths and handle empty-snippet case (ALLOW_RETRIES:1) backend:RISC-V tools:llvm-exegesis
#164924 opened Oct 24, 2025 by hank95179 Loading… updated Oct 26, 2025
[SLP] Prefer copyable vectorization over alternate opcodes backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#153684 opened Aug 14, 2025 by alexey-bataev Loading… updated Oct 14, 2025
[DAGCombiner] Set shift flags during visit. backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#91239 opened May 6, 2024 by goldsteinn • Draft updated Oct 2, 2025
Clang AST updates for more details backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category HLSL HLSL Language Support
#152372 opened Aug 6, 2025 by sei-nreimer Loading… updated Sep 18, 2025
[lldb] Implement RISCV function unwinding using instruction emulation backend:RISC-V lldb
#147434 opened Jul 8, 2025 by satyajanga • Draft updated Sep 12, 2025
[feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv backend:RISC-V llvm:binary-utilities llvm:mc Machine (object) code
#144620 opened Jun 18, 2025 by arjunUpatel Loading… updated Sep 5, 2025
[RISCV][TTI] Fix shift VV opcode mapping in getArithmeticInstrCost backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding
#156408 opened Sep 2, 2025 by steven-studio Loading… updated Sep 2, 2025
[RISC-V] Add SMLoc info for fixup. [NFCI] backend:RISC-V
#142054 opened May 29, 2025 by fpetrogalli Loading… updated Jun 7, 2025
[Asan][RISCV] Enhance getTgtMemIntrinsic() to allow Asan instrument t… backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#135198 opened Apr 10, 2025 by HankChang736 Loading… updated Apr 14, 2025
[Asan] Add TTI hook to provide memory reference information of target intrinsic. backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#133361 opened Mar 28, 2025 by HankChang736 Loading… updated Apr 7, 2025
[RISCV][MC] Implement ISA mapping symbols backend:RISC-V llvm:mc Machine (object) code
#67541 opened Sep 27, 2023 by joe-img Loading… updated Feb 18, 2025
[RISCV][DAG][TLI] Avoid scalarizing length decreasing shuffles backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#115532 opened Nov 8, 2024 by preames Loading… updated Dec 3, 2024
[llvm] Prefer StringRef::substr(0, N) to slice(0, N) (NFC) backend:ARM backend:PowerPC backend:RISC-V backend:X86 llvm:adt llvm:binary-utilities llvm:mc Machine (object) code llvm:support tablegen
#113793 opened Oct 27, 2024 by kazutakahirata Loading… updated Oct 31, 2024
[Asan][RISCV] Teach AddressSanitizer to support indexed load/store. backend:RISC-V compiler-rt:sanitizer llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms
#100930 opened Jul 28, 2024 by yetingk Loading… updated Aug 8, 2024
[RISCV] Support select optimization backend:RISC-V
#80124 opened Jan 31, 2024 by wangpc-pp Loading… updated Jul 5, 2024
[llvm][CodeGen] Added a check in CodeGenPrepare::optimizeSwitchType backend:RISC-V
#83322 opened Feb 28, 2024 by karouzakisp Loading… updated May 20, 2024
Implementation of '#pragma STDC FENV_ROUND' backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#89617 opened Apr 22, 2024 by spavloff Loading… updated May 17, 2024
[RISCV] Optimize pattern SelectionDAGISel as well
(setcc (selectLT (vfirst_vl ...) , 0, EVL, ...), EVL) backend:RISC-V llvm:ir llvm:SelectionDAG #90538 opened Apr 30, 2024 by mshockwave Loading… updated May 17, 2024
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