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Pull requests list

Clang: Add nsz to llvm.minnum and llvm.maxnum emitted from fmin and fmax backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category floating-point Floating-point math llvm:ir
#113133 opened Oct 21, 2024 by wzssyqa Loading… updated Dec 5, 2025
41
[RISCV64] liveness analysis backend:RISC-V llvm:regalloc
#167454 opened Nov 11, 2025 by hiraditya Loading… updated Dec 5, 2025
32
[IR] Split vector.splice into vector.splice.down and vector.splice.up backend:AArch64 backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#170796 opened Dec 5, 2025 by lukel97 Loading… updated Dec 5, 2025
4
[RISCV]: Implemented softening of FCANONICALIZE backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169234 opened Nov 23, 2025 by kper Loading… updated Dec 5, 2025
1
21
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#170076 opened Dec 1, 2025 by rez5427 Loading… updated Dec 5, 2025
16
[RISCV] Introduce a new tune feature string syntax and its parser backend:RISC-V tablegen
#168160 opened Nov 15, 2025 by mshockwave Loading… updated Dec 5, 2025
34
[RISCV][GISel] Legalize the G_FCANONICALIZE instruction backend:RISC-V llvm:globalisel
#166162 opened Nov 3, 2025 by circYuan Loading… updated Dec 5, 2025
3
[RISCV] Add Svrsw60t59b extension backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang Clang issues not falling into any other category llvm:mc Machine (object) code
#132321 opened Mar 21, 2025 by trdthg Loading… updated Dec 5, 2025
13
[RISCV][WIP] Let RA do the CSR saves. backend:RISC-V
#90819 opened May 2, 2024 by mgudim Loading… updated Dec 5, 2025
78
[RISCV] LMUL lists for indexed and strided loads backend:RISC-V
#169756 opened Nov 27, 2025 by ppenzin Loading… updated Dec 4, 2025
14
[RISCV] Use Zilsd Pseudos in ISel backend:RISC-V
#169580 opened Nov 25, 2025 by lenary Loading… updated Dec 4, 2025
9
[RISCV][LLD] Zcmt RISC-V extension in lld backend:RISC-V lld:ELF lld
#163142 opened Oct 13, 2025 by RobinKastberg Loading… updated Dec 4, 2025
5 of 8 tasks
27
[RISCV] Update P extension to the 018 version of the spec. backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
#170399 opened Dec 3, 2025 by topperc Loading… updated Dec 4, 2025
5
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading… updated Dec 4, 2025
1
[DAG] Fold mul 0 -> 0 when expanding mul into parts. backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#168780 opened Nov 19, 2025 by davemgreen Loading… updated Dec 4, 2025
13
[RISCV] Implement RVV scheduling model for andes 45 series processor. backend:RISC-V
#167821 opened Nov 13, 2025 by tclin914 Loading… updated Dec 4, 2025
21
[docs] [RISCV] Update docs regarding RV32E/RV64E backend:RISC-V
#170707 opened Dec 4, 2025 by RobinKastberg Loading… updated Dec 4, 2025
4
[WIP][CodeGen][DebugInfo][RISCV] Support scalable offsets in CFI backend:RISC-V debuginfo llvm:codegen llvm:mc Machine (object) code
#170607 opened Dec 4, 2025 by ppenzin Loading… updated Dec 4, 2025
4
[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC backend:RISC-V
#170726 opened Dec 4, 2025 by topperc Loading… updated Dec 4, 2025
1
[clang][DebugInfo] Add virtual call-site target information in DWARF. backend:AArch64 backend:ARM backend:MIPS backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo lldb llvm:binary-utilities llvm:codegen llvm:ir
#167666 opened Nov 12, 2025 by CarlosAlbertoEnciso Loading… updated Dec 4, 2025
@CarlosAlbertoEnciso
47
[RISCV][Zicfilp] Enable Zicfilp CFI compiler behaviors by looking at module flags backend:RISC-V llvm:support
#152121 opened Aug 5, 2025 by mylai-mtk Loading… updated Dec 4, 2025
25
[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading… updated Dec 4, 2025
30
[VPlan] Use nuw/nsw when computing {VF,VScale}xUF backend:RISC-V llvm:transforms vectorizers
#170710 opened Dec 4, 2025 by artagnon Loading… updated Dec 4, 2025
2
[CodeGen] Allow multiple location for the same CSR. backend:RISC-V llvm:codegen
#168531 opened Nov 18, 2025 by mgudim Loading… updated Dec 4, 2025
5
[RISCV] Update Zvqdotq to v0.1 backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
#170648 opened Dec 4, 2025 by wangpc-pp Loading… updated Dec 4, 2025
12
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