- Notifications
You must be signed in to change notification settings - Fork 15.4k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[RISCV] Make RISCVInstrInfo::verifyInstruction stricter for immediate-only operands backend:RISC-V tools:llvm-exegesis
#170736 by topperc was merged Dec 4, 2025 Loading…
[RISCV] Inserting indirect jumps with X7 for Zicfilp backend:RISC-V
#170683 by jaidTw was merged Dec 5, 2025 Loading…
[RISCV] Emit lpad for function with returns-twice attribute backend:RISC-V
#170520 by jaidTw was merged Dec 4, 2025 Loading…
[RISCV][NFC] Simplify Imm range checks backend:RISC-V
#170497 by pfusik was merged Dec 4, 2025 Loading…
[RISCV] Sources of vmerge shouldn't overlap V0 backend:RISC-V llvm:globalisel
#170070 by wangpc-pp was merged Dec 3, 2025 Loading…
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 by arcbbb was merged Dec 4, 2025 Loading…
[RISCV] Omit VTYPE in VSETVLIInfo::print() when state is uninit or unknown. backend:RISC-V
#169459 by topperc was merged Nov 25, 2025 Loading…
[RISCV] Use vsetivli instead of
x0,x0 form to retain SEW/LMUL when AVL is imm backend:RISC-V #169307 by wangpc-pp was closed Dec 4, 2025 Loading…
[RISCV][ISelLowering] Use Zicond for FP selects on Zfinx/Zdinx backend:RISC-V
#169299 by fennecJ was merged Dec 1, 2025 Loading…
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading…
[llvm][RISCV] Handle atomic and volatile in ZilsdOptimizer backend:RISC-V
#169169 by 4vtomat was closed Nov 22, 2025 Loading…
[RISCV] Remove custom isel lowering of i64 to Zilsd load/store. backend:RISC-V
#169067 by topperc was closed Nov 25, 2025 Loading…
[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit truncation exists backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#169022 by XChy was merged Nov 21, 2025 Loading…
[VPlan] Drop poison-generating flags on induction trunc backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168922 by artagnon was merged Nov 21, 2025 Loading…
Reapply "[LV] Use ExtractLane(LastActiveLane, V) live outs when tail-folding. (#149042)" backend:RISC-V llvm:transforms vectorizers
#168738 by lukel97 was closed Nov 26, 2025 Loading…
[TTI] Use MemIntrinsicCostAttributes for getGatherScatterOpCost backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#168650 by arcbbb was merged Dec 3, 2025 Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms LTO Link time optimization (regular/full LTO or ThinLTO)
#168622 by arsenm was merged Dec 3, 2025 Loading…
CodeGen: Move libcall lowering configuration to subtarget backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168621 by arsenm was merged Nov 25, 2025 Loading…
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager backend:RISC-V
#168381 by asb was merged Nov 19, 2025 Loading…
[VPlan] Skip uses-scalars restriction if one of ops needs broadcast. backend:RISC-V llvm:transforms vectorizers
#168246 by fhahn was merged Nov 28, 2025 Loading…
[RISCV][llvm] Select splat_vector(constant) with PLI backend:RISC-V
#168204 by 4vtomat was merged Nov 20, 2025 Loading…
[Clang][CodeGen] Add disable_sanitizer_instrumentation attribute to multiversion resolvers backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category compiler-rt:sanitizer compiler-rt:tsan Thread sanitizer compiler-rt
#167516 by BStott6 was merged Nov 12, 2025 Loading…
Revert "[VPlan] Handle WidenGEP in narrowToSingleScalars" backend:RISC-V llvm:transforms vectorizers
#167509 by artagnon was merged Nov 11, 2025 Loading…
[RISCV] Remove intrinsic declarations in tests, NFC backend:RISC-V llvm:globalisel
#167474 by jacquesguan was merged Nov 26, 2025 Loading…
Remove unused standard header inclusion: <iterator>, <utility>, <type_traits> backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:RISC-V backend:SPIR-V backend:SystemZ backend:X86 debuginfo llvm:adt llvm:analysis Includes value tracking, cost tables and constant folding llvm:binary-utilities llvm:codegen llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:ir llvm:mc Machine (object) code llvm:regalloc llvm:support llvm:transforms PGO Profile Guided Optimizations platform:windows tablegen tools:llvm-exegesis xray
#167318 by serge-sans-paille was closed Nov 11, 2025 Loading…
Previous Next
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.