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Pull requests: llvm/llvm-project

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CodeGen: Move libcall lowering configuration to subtarget backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG

SelectionDAGISel as well

#168621 by arsenm was merged Nov 25, 2025

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CodeGen: Add subtarget to TargetLoweringBase constructor backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG

SelectionDAGISel as well

#168620 by arsenm was merged Nov 19, 2025

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[ARM][BPF][Lanai][MSP430] Use MCRegister::id() to avoid an implicit cast. NFC backend:ARM backend:Lanai backend:MSP430

#167537 by topperc was merged Nov 11, 2025

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MSP430: Remove more default compiler-rt calls backend:MSP430 llvm:ir

#164752 by arsenm was merged Oct 23, 2025

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[NFC] "unsafe-fp-math" post cleanup (code comments part) backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 clang:openmp

OpenMP related changes to Clang

coroutines

C++20 coroutines

debuginfo lld:COFF lld:MachO lld:wasm lld llvm:analysis

Includes value tracking, cost tables and constant folding

llvm:binary-utilities llvm:globalisel llvm:instcombine

Covers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:SelectionDAG

SelectionDAGISel as well

llvm:transforms LTO

Link time optimization (regular/full LTO or ThinLTO)

PGO

Profile Guided Optimizations

#164582 by paperchalice was merged Oct 22, 2025

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[IR][CodeGen] Remove unsafe-fp-math attribute support backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 clang:codegen

IR generation bugs: mangling, exceptions, etc.

clang:openmp

OpenMP related changes to Clang

clang

Clang issues not falling into any other category

compiler-rt:sanitizer coroutines

C++20 coroutines

debuginfo lld:COFF lld:MachO lld:wasm lld llvm:analysis

Includes value tracking, cost tables and constant folding

llvm:binary-utilities llvm:codegen llvm:globalisel llvm:instcombine

Covers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:ir llvm:SelectionDAG

SelectionDAGISel as well

llvm:transforms LTO

Link time optimization (regular/full LTO or ThinLTO)

PGO

Profile Guided Optimizations

#164400 by paperchalice was closed Oct 22, 2025

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CodeGen: Make all targets override pseudos with pointers backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:mc

Machine (object) code

llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#159881 by arsenm was merged Nov 26, 2025

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CodeGen: Remove TRI arguments from stack load/store hooks backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#158240 by arsenm was merged Nov 11, 2025

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CodeGen: Remove TRI argument from reMaterialize backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#158229 by arsenm was merged Nov 11, 2025

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ARM: Remove TRI argument from AddDReg backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#158228 by arsenm was merged Nov 10, 2025

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CodeGen: Remove TRI argument from getRegClass backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#158225 by arsenm was merged Nov 10, 2025

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CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#158224 by arsenm was merged Nov 10, 2025

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CodeGen: Remove MachineFunction argument from getRegClass backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc llvm:SelectionDAG

SelectionDAGISel as well

#158188 by arsenm was merged Sep 12, 2025

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CodeGen: Remove MachineFunction argument from getPointerRegClass backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel

#158185 by arsenm was merged Sep 12, 2025

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[llvm] Move data layout string computation to TargetParser backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:ir

#157612 by rnk was merged Sep 11, 2025

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CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen tablegen

#157337 by arsenm was merged Sep 8, 2025

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MSP430: Do not add target specific STI member to MSP430AsmParser backend:MSP430

#156443 by arsenm was merged Sep 2, 2025

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[NFC][MC][MSP430] Rearrange decoder functions for MSP430 disassembler backend:MSP430

#155011 by jurahul was merged Aug 25, 2025

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[NFC][MC][Decoder] Extract fixed pieces of decoder code into new header file backend:AArch64 backend:AMDGPU backend:ARC backend:ARM backend:CSKY backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:Xtensa llvm:mc

Machine (object) code

tablegen

#154802 by jurahul was merged Aug 21, 2025

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[Target] Remove SoftFail field on targets that don't use it (NFC) backend:AMDGPU backend:ARC backend:CSKY backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SystemZ backend:Xtensa

#154659 by s-barannikov was merged Aug 21, 2025

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MSP430: Move __mspabi_mpyll calling conv config to tablegen backend:MSP430 llvm:ir

#153988 by arsenm was merged Aug 19, 2025

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[NFC] RuntimeLibcalls: Prefix the impls with 'Impl_' backend:ARM backend:MIPS backend:MSP430 backend:Sparc llvm:codegen llvm:ir tablegen

#153850 by dpaoliello was merged Sep 2, 2025

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[CodeGen] Provide original IR type to CC lowering (NFC) backend:AArch64 backend:ARM backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:globalisel llvm:SelectionDAG

SelectionDAGISel as well

tablegen

#152709 by nikic was merged Aug 11, 2025

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[Test] Add and update tests for lrint/llrint (NFC) backend:AArch64 backend:ARM backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86

#152662 by tgross35 was merged Aug 12, 2025

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MCAsmBackend::applyFixup: Change Data to indicate the relocated location backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:mc

Machine (object) code

#151724 by MaskRay was closed Aug 2, 2025

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