- Notifications
You must be signed in to change notification settings - Fork 15.3k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[VPlan] Explicitly unoll replicate-regions without live-outs by VF. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170212 opened Dec 1, 2025 by fhahn Loading…
[LV][NFC] Remove unnecessary multiply in expandVPWidenIntOrFpInduction backend:RISC-V llvm:transforms vectorizers
#170159 opened Dec 1, 2025 by david-arm Loading…
[SelectionDAG] Lowering usub.sat(a, 1) to a - (a != 0) backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#170076 opened Dec 1, 2025 by rez5427 Loading…
[RISCV][llvm] Support PSLL codegen for P extension backend:RISC-V
#170074 opened Dec 1, 2025 by 4vtomat Loading…
[RISCV] Sources of vmerge shouldn't overlap V0 backend:RISC-V llvm:globalisel
#170070 opened Dec 1, 2025 by wangpc-pp Loading…
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading…
[llvm-exegesis] Make rvv/filter.test deterministic backend:RISC-V tools:llvm-exegesis
#170014 opened Nov 29, 2025 by boomanaiden154 Loading…
[RISCV] Update SpacemiT-X60 vector load/stores backend:RISC-V
#169936 opened Nov 28, 2025 by mikhailramalho Loading…
GlobalISel: Stop using TPC to check if GlobalISelAbort is enabled backend:RISC-V llvm:globalisel
#169917 opened Nov 28, 2025 by petar-avramovic Loading…
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading…
[RISCV][GISel] Fix legalize G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169877 opened Nov 28, 2025 by jacquesguan Loading…
[RISCV][GISel] Support select G_EXTRACT_SUBVECTOR backend:RISC-V llvm:globalisel
#169789 opened Nov 27, 2025 by jacquesguan Loading…
[RISCV] LMUL lists for indexed and strided loads backend:RISC-V
#169756 opened Nov 27, 2025 by ppenzin Loading…
[Exegesis][RISCV] Support C_LDSP for llvm-exegesis backend:RISC-V tools:llvm-exegesis
#169660 opened Nov 26, 2025 by sunshaoce Loading…
[RISCV] Only convert volatile i64 load/store to Zilsd in SelectionDAG. backend:RISC-V
#169529 opened Nov 25, 2025 by topperc Loading…
optimize SelectionDAGISel as well
is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG #169402 opened Nov 24, 2025 by folkertdev Loading…
[RISCV] Use vsetivli instead of
x0,x0 form to retain SEW/LMUL when AVL is imm backend:RISC-V #169307 opened Nov 24, 2025 by wangpc-pp Loading…
[RISCV]: Implemented softening of SelectionDAGISel as well
FCANONICALIZE backend:RISC-V llvm:SelectionDAG #169234 opened Nov 23, 2025 by kper Loading…
[llvm][RISCV] Make X0 register pair legal in pre-ra pass backend:RISC-V
#169164 opened Nov 22, 2025 by 4vtomat Loading…
[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading…
[RISCV] Expand
X * (2^N - 2^M) where N < M backend:RISC-V #168843 opened Nov 20, 2025 by pfusik Loading…
[DAG] Fold mul 0 -> 0 when expanding mul into parts. backend:AArch64 backend:RISC-V llvm:SelectionDAG SelectionDAGISel as well
#168780 opened Nov 19, 2025 by davemgreen Loading…
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading…
[RISCV] Mark sincos libcalls as available for RISC-V backend:RISC-V llvm:ir
#168708 opened Nov 19, 2025 by asb Loading…
Previous Next
ProTip! Filter pull requests by the default branch with base:main.