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Pull requests: llvm/llvm-project
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[TRI] Remove reserved registers in getRegPressureSetLimit backend:AMDGPU backend:ARM backend:loongarch backend:NVPTX backend:PowerPC backend:X86 llvm:globalisel llvm:regalloc llvm:transforms tablegen
#118787 opened Dec 5, 2024 by wangpc-pp Loading…
[AIX] Implement the ifunc attribute. backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category compiler-rt:builtins compiler-rt llvm:codegen llvm:ir llvm:transforms
#153049 opened Aug 11, 2025 by w2yehia Loading…
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading…
[clang][analyzer][NFC] Run libclang and C++ API clang:codegen IR generation bugs: mangling, exceptions, etc. clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:modules C++20 modules and Clang Header Modules clang:openmp OpenMP related changes to Clang clang:static analyzer clang Clang issues not falling into any other category debuginfo HLSL HLSL Language Support
modernize-use-using check over all the code backend:AMDGPU backend:MIPS backend:PowerPC clang:analysis clang:as-a-library #149934 opened Jul 21, 2025 by localspook Loading…
[PowerPC] Enable indiviual crbits tracking at -O2 backend:PowerPC clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#133617 opened Mar 30, 2025 by mustartt Loading…
[SimplifyCFG] Emit SelectInst when folding branches to common dest with different PHI incoming values backend:AArch64 backend:PowerPC backend:X86 clang Clang issues not falling into any other category llvm:transforms vectorizers
#144434 opened Jun 16, 2025 by HighW4y2H3ll Loading…
AMDGPU: Drop and upgrade llvm.amdgcn.atomic.csub/cond.sub to atomicrmw backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:loongarch backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 clang:openmp OpenMP related changes to Clang flang:openmp llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms mlir:llvm mlir
#105553 opened Aug 21, 2024 by anjenner Loading…
[DAGCombiner] Set shift flags during visit. backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#91239 opened May 6, 2024 by goldsteinn • Draft
[SelectionDAG] Add SelectionDAGISel as well
f16 soft promotion for lrint and lround backend:AArch64 backend:ARM backend:loongarch backend:MIPS backend:MSP430 backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:SelectionDAG #152684 opened Aug 8, 2025 by tgross35 Loading…
[SDAG] Drop select -> fmax/min folding in SelectionDAGBuilder backend:AArch64 backend:AMDGPU backend:ARM backend:PowerPC backend:SystemZ llvm:SelectionDAG SelectionDAGISel as well
#93575 opened May 28, 2024 by dtcxzyw Loading…
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading…
[PowerPC] support tail call optimization on AIX tail call backend:PowerPC
#161690 opened Oct 2, 2025 by diggerlin Loading…
[llvm][test] Fix filecheck annotation typos [2/n] backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:m68k backend:NVPTX backend:PowerPC backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 coroutines C++20 coroutines debuginfo llvm:analysis Includes value tracking, cost tables and constant folding llvm:binary-utilities llvm:globalisel llvm:mc Machine (object) code llvm:transforms PGO Profile Guided Optimizations
#95433 opened Jun 13, 2024 by klensy Loading…
[PowerPC] Fix lowering when performing conditional jumps on f128 or f16 backend:PowerPC
#125776 opened Feb 4, 2025 by liushuyu Loading…
[MachinePipeliner] Add validation for missed dependencies backend:AArch64 backend:Hexagon backend:PowerPC
#135148 opened Apr 10, 2025 by kasuga-fj Loading…
[MachinePipeliner] Fix loop-carried dependencies analysis backend:AArch64 backend:Hexagon backend:PowerPC
#121907 opened Jan 7, 2025 by kasuga-fj Loading…
DAG: Handle load in SimplifyDemandedVectorElts backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:NVPTX backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#122671 opened Jan 13, 2025 by arsenm Loading…
[SelectionDAG] Fold (icmp eq/ne (shift X, C), 0) -> (icmp eq/ne X, 0) backend:ARM backend:PowerPC llvm:SelectionDAG SelectionDAGISel as well
#88801 opened Apr 15, 2024 by bjope Loading…
[PPC] generate stxvw4x/lxvw4x on P7 backend:PowerPC
#87049 opened Mar 29, 2024 by chenzheng1030 Loading…
[FPEnv][PowerPC] Correct one more strictfp test. backend:PowerPC
#94793 opened Jun 7, 2024 by kpneal Loading…
[DAGCombiner] Combine frem into fdiv+ftrunc+fma backend:AArch64 backend:PowerPC backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#67642 opened Sep 28, 2023 by ecnelises Loading…
[GlobalIsel] Avoid aligning alloca size. backend:AArch64 backend:PowerPC backend:SystemZ backend:X86 llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#132064 opened Mar 19, 2025 by jcogan-nv Loading…
[PowerPC] set libcall lowering for fp setcc ops on SPE boards backend:PowerPC
#153238 opened Aug 12, 2025 by Varnike Loading…
[PowerPC][AIX] Specify correct ABI alignment for double backend:PowerPC clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir
#144673 opened Jun 18, 2025 by nikic Loading…
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading…
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