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Pull requests list

[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading… updated Dec 2, 2025
22
[InferAlignment] Enhance alignment propagation for and(ptrtoint, const) pattern. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ clang Clang issues not falling into any other category coroutines C++20 coroutines llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#166935 opened Nov 7, 2025 by egorshamshura Loading… updated Dec 2, 2025
63
PowerPC/VSX: Select FMINNUM and FMAXNUM backend:PowerPC llvm:SelectionDAG SelectionDAGISel as well
#135739 opened Apr 15, 2025 by wzssyqa • Draft updated Dec 2, 2025
15
[PowerPC][AIX] Specify correct ABI alignment for double backend:PowerPC clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:ir
#144673 opened Jun 18, 2025 by nikic Loading… updated Dec 2, 2025
1
22
[PowerPC] Use the same lowering rule for vector rounding instructions backend:PowerPC
#166307 opened Nov 4, 2025 by paperchalice Loading… updated Dec 2, 2025
5
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading… updated Dec 2, 2025
10 tasks
6
Reland "[LICM] Sink unused l-invariant loads in preheader #157559" backend:AMDGPU backend:PowerPC llvm:transforms
#170204 opened Dec 1, 2025 by VigneshwarJ Loading… updated Dec 2, 2025
4
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
21
[PowerPC] cost modeling for length type VP intrinsic load/store backend:PowerPC llvm:analysis Includes value tracking, cost tables and constant folding
#168938 opened Nov 20, 2025 by RolandF77 Loading… updated Dec 1, 2025
16
[VPlan] Extract reverse operation for reverse accesses backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#146525 opened Jul 1, 2025 by Mel-Chen Loading… updated Dec 1, 2025
116
[SCEV] Add initial support for ptrtoaddr. backend:PowerPC llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir llvm:transforms
#158032 opened Sep 11, 2025 by fhahn Loading… updated Dec 1, 2025
16
[PowerPC] Remove NoInfsFPMath uses backend:PowerPC
#163029 opened Oct 12, 2025 by paperchalice Loading… updated Nov 28, 2025
1
[PowerPC] support tail call optimization on AIX tail call backend:PowerPC
#161690 opened Oct 2, 2025 by diggerlin Loading… updated Nov 27, 2025
3
optimize is_finite assembly backend:AArch64 backend:AMDGPU backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#169402 opened Nov 24, 2025 by folkertdev Loading… updated Nov 27, 2025
1
13
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading… updated Nov 27, 2025
39
[PowerPC] Add initial support for AMO load builtins backend:PowerPC backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category llvm:ir
#168746 opened Nov 19, 2025 by maryammo Loading… updated Nov 26, 2025
5
CodeGen: Add LibcallLoweringInfo analysis pass backend:AArch64 backend:AMDGPU backend:loongarch backend:PowerPC backend:RISC-V backend:SPIR-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:transforms
#168622 opened Nov 18, 2025 by arsenm Loading… updated Nov 26, 2025
21
[PowerPC] Add AMO load signed builtins backend:PowerPC backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category
#168747 opened Nov 19, 2025 by maryammo Loading… updated Nov 25, 2025
1
[RegisterCoalescer] Improve register allocation for return values by limiting rematerialization backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:X86 clang Clang issues not falling into any other category debuginfo llvm:codegen llvm:regalloc
#163047 opened Oct 12, 2025 by rez5427 Loading… updated Nov 25, 2025
32
[RISCV] Add optimization for memset inline backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#146673 opened Jul 2, 2025 by BoyaoWang430 Loading… updated Nov 25, 2025
16
[CodeGen] Add MachineRegisterClassInfo analysis pass backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen llvm:regalloc
#164877 opened Oct 23, 2025 by linuxrocks123 Loading… updated Nov 24, 2025
10
[PowerPC] Optimize not equal compares against zero vectors backend:PowerPC
#150422 opened Jul 24, 2025 by Himadhith Loading… updated Nov 24, 2025
45
[DAGCombiner] Honor rewrite semantics of fast-math flags in fdiv combine backend:AArch64 backend:AMDGPU backend:NVPTX backend:PowerPC backend:X86 floating-point Floating-point math llvm:SelectionDAG SelectionDAGISel as well
#167595 opened Nov 11, 2025 by mikolaj-pirog Loading… updated Nov 21, 2025
7
DAG: Handle load in SimplifyDemandedVectorElts backend:AArch64 backend:AMDGPU backend:ARM backend:loongarch backend:MIPS backend:NVPTX backend:PowerPC backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#122671 opened Jan 13, 2025 by arsenm Loading… updated Nov 12, 2025
9
[PowerPC] Add xor-not patterns to eqv backend:PowerPC
#165043 opened Oct 24, 2025 by AZero13 Loading… updated Oct 27, 2025
3
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