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Pull requests: llvm/llvm-project
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[VPlan] Extract reverse operation for reverse accesses backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#146525 opened Jul 1, 2025 by Mel-Chen Loading…
[IR] Add llvm SelectionDAGISel as well
clmul intrinsic backend:RISC-V llvm:ir llvm:SelectionDAG #140301 opened May 16, 2025 by oscardssmith Loading…
[SLPVectorizer] Widen strided loads. backend:RISC-V llvm:transforms vectorizers
#153074 opened Aug 11, 2025 by mgudim Loading…
[VPlan] Delay adding canonical IV increment. backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#82270 opened Feb 19, 2024 by fhahn Loading…
[LV] Support strided load with a stride of -1 backend:RISC-V llvm:transforms vectorizers
#128718 opened Feb 25, 2025 by Mel-Chen Loading…
[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:support mlgo
#151944 opened Aug 4, 2025 by vg0204 Loading…
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading…
[VPlan] Replace ExtractLast(Elem|LanePerPart) with ExtractLast(Lane/Part) backend:RISC-V llvm:transforms vectorizers
#164124 opened Oct 18, 2025 by fhahn Loading…
[LV][EVL] Generate negative strided load/store for reversed load/store backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#123608 opened Jan 20, 2025 by wangpc-pp Loading…
[LV] Convert gather loads with invariant stride into strided loads backend:RISC-V llvm:transforms vectorizers
#147297 opened Jul 7, 2025 by Mel-Chen Loading…
[InferAlignment] Enhance alignment propagation for and(ptrtoint, const) pattern. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ clang Clang issues not falling into any other category coroutines C++20 coroutines llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#166935 opened Nov 7, 2025 by egorshamshura Loading…
[SLP] Check for extracts, being replaced by original scalars, for user nodes backend:RISC-V llvm:transforms vectorizers
#149572 opened Jul 18, 2025 by alexey-bataev Loading…
[VPlan] Use BlockFrequencyInfo in getPredBlockCostDivisor backend:RISC-V llvm:transforms vectorizers
#158690 opened Sep 15, 2025 by lukel97 Loading…
[LV][VPlan] Add initial support for CSA vectorization backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#121222 opened Dec 27, 2024 by michaelmaitland Loading…
[clang][DebugInfo] Add virtual call-site target information in DWARF. backend:AArch64 backend:ARM backend:MIPS backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo lldb llvm:binary-utilities llvm:codegen llvm:ir
#167666 opened Nov 12, 2025 by CarlosAlbertoEnciso Loading…
[VPlan] Don't use the legacy cost model for loop conditions backend:RISC-V llvm:transforms vectorizers
#156864 opened Sep 4, 2025 by john-brawn-arm Loading…
[feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv backend:RISC-V llvm:binary-utilities llvm:mc Machine (object) code
#144620 opened Jun 18, 2025 by arjunUpatel Loading…
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading…
[VPlan] Enable vectorization of early-exit loops with unit-stride fault-only-first loads backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#151300 opened Jul 30, 2025 by arcbbb Loading…
[LV][RFC] Generating conditional VPBB that will be skip when the mask is inactive in VPlan. backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#141900 opened May 29, 2025 by ElvisWang123 Loading…
[RISCV] Optimize divide by constant for VP intrinsics backend:RISC-V llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#125991 opened Feb 6, 2025 by jaidTw Loading…
[LV]Enable non-power-of-2 store-load forwarding distance in predicated DataWithEVL vectorization mode backend:RISC-V llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#100755 opened Jul 26, 2024 by alexey-bataev Loading…
[Clang][IR] add TBAA metadata on pointer, union and array types. backend:AMDGPU backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category llvm:analysis Includes value tracking, cost tables and constant folding llvm:ir TBAA Type-Based Alias Analysis / Strict Aliasing
#75177 opened Dec 12, 2023 by dybv-sc Loading…
[VPlan] Use VPInstruction for uniform binops. backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#141429 opened May 25, 2025 by fhahn Loading…
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