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[AMDGPU] Serialize disjoint MFMA chains to hide DS_READ latency backend:AMDGPU
#170242 opened Dec 2, 2025 by gandhi56 Loading… updated Dec 2, 2025
[OpenCL][NVPTX] Don't set calling convention for OpenCL kernel backend:AMDGPU clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category
#170170 opened Dec 1, 2025 by XChy Loading… updated Dec 2, 2025
[AMDGPU] Apply alignment attr for make.buffer.rsrc backend:AMDGPU clang Clang issues not falling into any other category llvm:transforms
#166914 opened Nov 7, 2025 by Shoreshen Loading… updated Dec 2, 2025
[AMDGPU][GISel] Add RegBankLegalize support for G_STRICT_{FADD|FMUL} backend:AMDGPU llvm:globalisel
#169406 opened Nov 24, 2025 by chinmaydd Loading… updated Dec 2, 2025
[AMDGPU] Generate waterfall for calls with SGPR(inreg) argument backend:AMDGPU
#146997 opened Jul 4, 2025 by Shoreshen Loading… updated Dec 2, 2025
AMDGPU: Use ConstantPool as source value for DAG lowered kernarg loads backend:AMDGPU llvm:globalisel
#168917 opened Nov 20, 2025 by arsenm Loading… updated Dec 2, 2025
[mlir][amdgpu] Lower amdgpu.make_dma_base backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169817 opened Nov 27, 2025 by amd-eochoalo Loading… updated Dec 2, 2025
[AMDGPU] Allow any SGPRs for chain callees backend:AMDGPU llvm:globalisel
#168345 opened Nov 17, 2025 by rovka Loading… updated Dec 2, 2025
AMDGPU: Fix treating unknown mem operands as uniform backend:AMDGPU llvm:globalisel
#168980 opened Nov 21, 2025 by arsenm Loading… updated Dec 2, 2025
Reland "[LICM] Sink unused l-invariant loads in preheader #157559" backend:AMDGPU backend:PowerPC llvm:transforms
#170204 opened Dec 1, 2025 by VigneshwarJ Loading… updated Dec 2, 2025
[mlir][AMDGPU] Add scaled wmma ops for gfx1250 backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169854 opened Nov 27, 2025 by justinrosner Loading… updated Dec 2, 2025
[AMDGPU] Add Clang issues not falling into any other category llvm:ir
nocreateundeforpoison annotations backend:AMDGPU clang #166450 opened Nov 4, 2025 by krzysz00 Loading… updated Dec 2, 2025
VectorCombine: Improve the insert/extract fold in the narrowing case backend:AMDGPU llvm:transforms llvm:vectorcombine vectorizers
#168820 opened Nov 20, 2025 by nhaehnle Loading… updated Dec 2, 2025
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops backend:AMDGPU
#168964 opened Nov 20, 2025 by hjagasiaAMD Loading… updated Dec 1, 2025
VectorCombine: Fold chains of shuffles fed by length-changing shuffles backend:AMDGPU llvm:transforms llvm:vectorcombine vectorizers
#168819 opened Nov 20, 2025 by nhaehnle Loading… updated Dec 1, 2025
[AMDGPU] Reland "Remove leftover implicit operands from SI_SPILL/SI_RESTORE" backend:AMDGPU
#169449 opened Nov 25, 2025 by LU-JOHN Loading… updated Dec 1, 2025
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
[mlir][AMDGPU][NFC] Fix overlapping masked load refinements backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#159805 opened Sep 19, 2025 by krzysz00 Loading… updated Dec 1, 2025
[DAG] Use known-bits when creating umulh/smulh. backend:AMDGPU backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#160916 opened Sep 26, 2025 by davemgreen Loading… updated Dec 1, 2025
Avoid maxnum(sNaN, x) optimizations / folds backend:AMDGPU backend:ARM backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:SelectionDAG SelectionDAGISel as well llvm:transforms
#170181 opened Dec 1, 2025 by LewisCrawford Loading… updated Dec 1, 2025
Try To Guess SGMasks for Inline Asm Instructions backend:AMDGPU
#155491 opened Aug 26, 2025 by linuxrocks123 Loading… updated Dec 1, 2025
[SPIRV] Use AMDGPU ABI for AMDGCN flavoured SPIRV backend:AMDGPU backend:SPIR-V clang:codegen IR generation bugs: mangling, exceptions, etc.
#169865 opened Nov 28, 2025 by AlexVlx Loading… updated Dec 1, 2025
[mlir][amdgpu] Add lowering for make_dma_descriptor backend:AMDGPU mlir:amdgpu mlir:gpu mlir
#169955 opened Nov 28, 2025 by amd-eochoalo Loading… updated Dec 1, 2025
[IR] Add CallBr intrinsics support backend:AMDGPU llvm:globalisel llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms
#133907 opened Apr 1, 2025 by ro-i Loading… updated Dec 1, 2025
[AMDGPU] Invert scc uses to delete s_cmp_eq* backend:AMDGPU llvm:codegen
#167382 opened Nov 10, 2025 by LU-JOHN Loading… updated Dec 1, 2025
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