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Pull requests: llvm/llvm-project
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[VPlan] Directly unroll VectorPointerRecipe backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#168886 opened Nov 20, 2025 by artagnon Loading… updated Dec 2, 2025
[VPlan] Use BlockFrequencyInfo in getPredBlockCostDivisor backend:RISC-V llvm:transforms vectorizers
#158690 opened Sep 15, 2025 by lukel97 Loading… updated Dec 2, 2025
[CodeGen] Add MO_LaneMask type and a new COPY_LANEMASK instruction backend:AArch64 backend:AMDGPU backend:ARM backend:RISC-V llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:support mlgo
#151944 opened Aug 4, 2025 by vg0204 Loading… updated Dec 2, 2025
[DAG] Use known-bits when creating umulh/smulh. backend:AMDGPU backend:RISC-V backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#160916 opened Sep 26, 2025 by davemgreen Loading… updated Dec 2, 2025
Clang: Add nsz to llvm.minnum and llvm.maxnum emitted from fmin and fmax backend:RISC-V clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category floating-point Floating-point math llvm:ir
#113133 opened Oct 21, 2024 by wzssyqa Loading… updated Dec 2, 2025
[RISCV][llvm] Support PSLL codegen for P extension backend:RISC-V
#170074 opened Dec 1, 2025 by 4vtomat Loading… updated Dec 2, 2025
[RISCV] Schedule RVV instructions with compatible type first backend:RISC-V
#95924 opened Jun 18, 2024 by wangpc-pp Loading… updated Dec 2, 2025
[lldb][RISCV] Implement trap handler unwind plan backend:RISC-V lldb
#166531 opened Nov 5, 2025 by sga-sc Loading… updated Dec 2, 2025
[RISCV] Sources of vmerge shouldn't overlap V0 backend:RISC-V llvm:globalisel
#170070 opened Dec 1, 2025 by wangpc-pp Loading… updated Dec 2, 2025
[TTI] Remove masked/gather-scatter/strided/expand-compress costing from TTIImpl backend:AArch64 backend:ARM backend:Hexagon backend:RISC-V backend:X86 llvm:analysis Includes value tracking, cost tables and constant folding
#169885 opened Nov 28, 2025 by arcbbb Loading… updated Dec 2, 2025
[Exegesis][RISCV] Support C_LDSP for llvm-exegesis backend:RISC-V tools:llvm-exegesis
#169660 opened Nov 26, 2025 by sunshaoce Loading… updated Dec 2, 2025
GlobalISel: Stop using TPC to check if GlobalISelAbort is enabled backend:RISC-V llvm:globalisel
#169917 opened Nov 28, 2025 by petar-avramovic Loading… updated Dec 1, 2025
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
Refactor WIDE_READ to allow finer control over high-performance function selection backend:RISC-V bazel "Peripheral" support tier build system: utils/bazel libc
#165613 opened Oct 29, 2025 by Sterling-Augustine Loading… updated Dec 1, 2025
[RISCV] Use vsetivli instead of
x0,x0 form to retain SEW/LMUL when AVL is imm backend:RISC-V #169307 opened Nov 24, 2025 by wangpc-pp Loading… updated Dec 1, 2025
[VPlan] Explicitly unoll replicate-regions without live-outs by VF. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170212 opened Dec 1, 2025 by fhahn Loading… updated Dec 1, 2025
[RISCV] Use Zilsd Pseudos in ISel backend:RISC-V
#169580 opened Nov 25, 2025 by lenary Loading… updated Dec 1, 2025
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. backend:RISC-V backend:SystemZ llvm:transforms vectorizers
#170053 opened Nov 30, 2025 by fhahn Loading… updated Dec 1, 2025
[RISCV] Adopt SpacemitX60's scheduling model for
-mtune=generic backend:RISC-V llvm:globalisel #167008 opened Nov 7, 2025 by mshockwave Loading… updated Dec 1, 2025
[clang][DebugInfo] Add virtual call-site target information in DWARF. backend:AArch64 backend:ARM backend:MIPS backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo lldb llvm:binary-utilities llvm:codegen llvm:ir
#167666 opened Nov 12, 2025 by CarlosAlbertoEnciso Loading… updated Dec 1, 2025
[VPlan] Replace ExtractLast(Elem|LanePerPart) with ExtractLast(Lane/Part) backend:RISC-V llvm:transforms vectorizers
#164124 opened Oct 18, 2025 by fhahn Loading… updated Dec 1, 2025
[VPlan] Extract reverse operation for reverse accesses backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#146525 opened Jul 1, 2025 by Mel-Chen Loading… updated Dec 1, 2025
[LV][NFC] Remove unnecessary multiply in expandVPWidenIntOrFpInduction backend:RISC-V llvm:transforms vectorizers
#170159 opened Dec 1, 2025 by david-arm Loading… updated Dec 1, 2025
[InferAlignment] Enhance alignment propagation for and(ptrtoint, const) pattern. backend:AMDGPU backend:PowerPC backend:RISC-V backend:SystemZ clang Clang issues not falling into any other category coroutines C++20 coroutines llvm:analysis Includes value tracking, cost tables and constant folding llvm:globalisel llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#166935 opened Nov 7, 2025 by egorshamshura Loading… updated Dec 1, 2025
[LV] Convert gather loads with invariant stride into strided loads backend:RISC-V llvm:transforms vectorizers
#147297 opened Jul 7, 2025 by Mel-Chen Loading… updated Dec 1, 2025
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